Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Hui Xu

Toru Sano

Yasuki Tanabe

An operation device according to an embodiment includes an operation instruction circuit, an operation circuit, a buffer and a storage area instruction circuit. The operation instruction circuit issues an operation instruction for an operation type of either one of a first operation and a second operation. The operation circuit performs an operation in accordance with the operation instruction, and outputs an intermediate operation result. The buffer stores the intermediate operation result. The storage area instruction circuit specifies an area within the buffer in Which the intermediate operation result is stored, according to the operation type.

Operation device and operation system

According to one embodiment, a router includes a plurality of input ports and a plurality of output ports. The input ports receive a packet including control information indicating a type of access. Each of the input ports includes a first buffer and a second buffer which store the packet. The output ports output the packet. Each of the input ports selects at least one of the first buffer and the second buffer as a buffer in which the packet is stored on the basis of the control information and a state of the output port serving as a destination port of the packet.

Router and many-core system

According to one embodiment, a router manages routing of a packet transferred between a plurality of cores and at least one of cache memories to which the cores can access. The router includes an analyzer, a packet memory and a controller. The analyzer determines whether the packet is a read-packet or a write-packet. The packet memory stores at least part of the write-packet issued by one of the cores. The controller stores cache data of the write-packet and a cache address in the packet memory when the analyzer determines that the packet is the write-packet. The cache address indicates an address in which the cache data is stored. The controller outputs the cache data stored in the packet memory to the core issuing a read-request as a response data corresponding to the read packet when the analyzer determines that the packet is the read-packet and the cache address corresponding to the read-request is stored in the packet memory.

Growing community of inventors

Kanagawa, Japan

Hui Xu