University of California

Qualcomm Incorporated

Hui Wang

Patrick Mercier

Terence Cheung

Abdolreza Langari

Ching-Liou Huang

Yuan Li

Shrestha Ganguly

Gert Cauwenberghs

Debesh Bhatta

Christoph Hans Maier

John Abcarius

Sohmyung Ha

Chul Kim

Jiwoong Park

Shitong Zhao

Abraham Akinin

Sulin Li

An aspect of the disclosure relates to a reference voltage generator, including: a first field effect transistor (FET) including a first threshold voltage; a second FET including a second threshold voltage different than the first threshold voltage; a gate voltage generator coupled to gates of the first and second FETs; a first current source coupled in series with the first FET between first and second voltage rails; a second current source; and a first resistor coupled in series with the second current source and the second FET between the first and second voltage rails, wherein a reference voltage is generated across the first resistor.

Reference voltage generator based on threshold voltage difference of field effect transistors

A charging to digital converter sensor in a CMOS integrated circuit digitizes a sensed property by comparing charging time between two paths and adjusting the charging rate of one of the two paths by increasing or decreasing the amount of capacitance in that path, until both of the two paths have the same charging time to reach respective constant with sensed property and proportional with sensed property reference voltages or currents. Sub nanowatt operation is achieved with preferred circuits. A method directly digitizes, on-chip, a charging time comparison of two ramp voltages that are compared to respective constant with sensed property and proportional with sensed property reference voltages or currents.

Near zero power fully integrated digital conversion, sensors and sensing methods

A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.

Device comprising first solder interconnects aligned in a first direction and second solder interconnects aligned in a second direction

An ultra-low-power voltage reference generator in an integrated CMOS circuit includes a regular MOS transistor reference current source connected to a line voltage and a regular MOS transistor resistor between the regular MOS transistor reference current source and ground. A constant with temperature reference voltage VREF is generated from a terminal inter-connecting the regular MOS transistor reference current source and the regular MOS transistor resistor. An ultra-low-power current reference generator receives a reference voltage and generated ultra-low level current from the reference voltage with a temperature compensated gate-leakage array.

Stabilized voltage and current reference generator and circuits

A charging to digital converter sensor in a CMOS integrated circuit includes a sensor responding to a sensed property, a converter that converts the sensed property into a charging time, a digitizer for digitizing the charging time, and digital feedback to reset the converter to restart the charging time. Preferred methods for sensing match the rising time of the first ramp voltage to a second ramp voltage generated by a reference current mirrored from a common current generator via the tuning of DAC capacitors driven by an LSB-first SAR logic feedback; or match rising times of the first and second ramp voltages to a reference voltage and providing a digital signal that translates the relationship of the first ramp voltage and the reference voltage to a digital quantification of the sensed property.

Near zero power charging to digital converter, sensors and sensing methods

In one respect, there is provided an apparatus for neural stimulation. The apparatus may include an antenna, a plurality of electrodes, and a voltage supply generator. The antenna may be configured to receive, from an external source, radio frequency energy. The voltage supply generator configured to generate a voltage supply by at least ramping up a voltage of the radio frequency energy in successive increments, wherein the voltage supply drives a current to the plurality of electrodes during neural stimulation. Related methods and computer program products are also disclosed.

Radio frequency powered adiabatic stimulation with energy replenishment

Growing community of inventors

La Jolla, CA, United States of America

Hui Wang