Marvell International Limited

Marvell Asia Pte., Ltd.

Headway Technologies, Incorporated

Geron Corporation

Cisco Technology, Inc.

Omnivision Technologies, Inc.

Black Sesame Technologies Inc.

Marvellworld Trade Ltd.

Hui Wang

Yonghua Song

Xin Ma

William Lo

Runsheng He

Haoli Qian

Ping Zheng

Yi-Chun Chen

Wenjie Li

Jianmin Guo

Jeffrey Choun

Jingjing Deng

Min Li

Kunliang Zhang

Tong Zhao

Chee Hoe Chu

Zubir Adal

Runzi Chang

Arivu Mani Ramasamy

Yu-Hsia Chen

Arindam Paul

Michael A DeMoney

Wei-Feng Huang

Yihui Li

Bart Burington

Yuguo Ye

Fei Guo

Hong Xue

Jeff Hsieh

Pilong Gao

Ekaterina Bassett

Changguo Shen

Kevin Eng

Tao Zhang

Zheng Li

Ying Zhou

Zheng Qi

Yi Wang

Zhu Zhen Pirot

Ning F Go

Yanfang Huang

Xuemei Liu

Chee Hoa Chu

Jingyuan Li

The present invention relates to an image warping system capable of quickly performing image warping with low costs by using a cache memory, and a method thereof. The image warping system is provided to generate a transformed image by warping an input image with the help of a cache based WARP engine. The WARP engine accesses the input image and loads a portion of the image to the cache memory for speeding up the engine process. The WARP engine performs interpolation on the input image to generate an output image which is devoid of distortions. The output image obtained is then stored in the DDR of an electronic device.

Cache-based warp engine

An extensible multi-precision data pipeline system, comprising, a local buffer that stores an input local data set in a local storage format, an input tensor shaper coupled to the local buffer that reads the input local data set and converts the input local data set into an input tensor data set having a tensor format of vector width N by tensor length L, a cascaded pipeline coupled to the input tensor shaper that routes the input tensor data set through at least one function stage resulting in an output tensor data set, an output tensor shaper coupled to the cascaded pipeline that converts the output tensor data set into an output local data set having the local storage format and wherein the output tensor shaper writes the output local data set to the local buffer.

Extensible multi-precision data pipeline for computing non-linear and arithmetic functions in artificial neural networks

Aspects of the disclosure provide a receiver for receiving data over a wired communication channel. The receiver includes an analog front end circuit, a pulse generation circuit and a voltage-controlled oscillator (VCO). The analog front end circuit receives an analog signal carrying data over the wired communication channel, and outputs a data signal with data bit transitions between voltage levels. The pulse generation circuit generates a pulse signal in response to the data bit transitions in the data signal. The voltage-controlled oscillator (VCO) generates an oscillation signal for providing sampling clocks for the data signal. The voltage-controlled oscillator aligns transitions in the oscillation signal to the pulse signal by forcing the oscillation signal to transit voltage levels in response to a pulse in the pulse signal.

Method and apparatus for clock recovery

A short-reach data link receiver includes an edge detector configured to generate a pulse on an edge of a data input, a first clock-data recovery path coupled to an output of the edge detector for recovering a clock and data from the output of the edge detector, a second clock-data recovery path coupled to the output of the edge detector for recovering the clock and data from the output of the edge detector, and a controller configured to alternate between the first and second clock-data recovery paths to recover the clock and data using one of the paths while calibrating the other path. The controller may swap the paths whenever calibration of one path is completed. That may include beginning calibration of the next path immediately after swapping of the paths. Alternatively, power consumption may be reduced by delaying calibration of the next path after swapping of the paths.

Oscillator calibration structure and method

A clock-data recovery circuit includes a variable data path delay, an injection-locked oscillator having a free-running frequency, and circuitry for adjusting at least one of the variable data path delay and the free-running frequency, including a counter configured to count repetitions of a bit value in an input data signal, and further being configured to, on occurrence of a first data pattern in the input data signal, indicative of saturation of inter-symbol interference, measure the input data signal at a first clock edge to determine a first data phase measurement value, measure the input data signal at clock centers immediately preceding and immediately following the first clock edge to determine second and third data phase measurement values, and based on first predetermined relationships among the first, second and third data phase measurement values, adjust the variable data path.

Phase and frequency control for clock-data recovery

A method of forming a finFET includes providing a semiconductor substrate having at least one fin feature extending through a diffusion layer formed on the semiconductor substrate, forming a gate layer on the diffusion layer and the fin feature, splitting the gate layer into a split gate structure including a first gate region, a second gate region, and a gap separating the first gate region and the second gate region, doping the gate layer, doping the diffusion layer to form a plurality of source/drain regions that includes a source/drain region in the gap between the first gate region and the second gate region, and injecting dopants into the diffusion layer to form a diffusion region having a plurality of pocket dopant regions. The plurality of pocket dopant regions includes at least one pocket dopant region in the gap between the first gate region and the second gate region.

Systems and methods for forming finFET analog designs having a modular memory-like layout

A low-power transmitter for transmitting digital signals from an integrated chip is described herein. The transmitter includes a voltage-mode transmitter driver comprised of a plurality of driver slices, which includes an up-cell having a first resistor and a first transistor, and a down-cell having a second resistor, a second transistor, and a third transistor. A calibration circuit drives a replica circuit to a desired impedance by adjusting a first gate voltage applied to the first transistor of the replica of the up-cell and adjusting a second gate voltage applied to the third transistor of the replica of the down-cell. The calibrated first gate voltage is applied to the first transistor and to the second transistor of each of the plurality of driver slices and the calibrated second gate voltage is applied to the third transistor of each of the plurality of driver slices.

Systems and methods for calibrating impedance of a low power voltage-mode transmitter driver

Systems for calibrating impedances caused by a first component and a second component of a voltage-mode transmitter driver are described herein. The first component includes a first transistor and a first resistor connected to the first transistor, wherein the first component is connected to a voltage source and an output end of the voltage-mode transmitter driver, respectively. The second component includes a second transistor and a second resistor connected to the second transistor, wherein the second component is connected to the output end of the voltage-mode transmitter driver, and a third transistor, respectively. A first gate of the third transistor is applied with a first tunable gate voltage, and the first tunable gate voltage is configured to be tuned to calibrate a first impedance between the output end and a ground to match with a second impedance between the voltage source and the output end.

A fin field effect transistor (finFET) includes a semiconductor substrate including at least one fin feature, a diffusion region formed on the semiconductor substrate and extending through the diffusion region, and a gate formed on the diffusion region and the at least one fin feature. The gate includes a split gate structure including a first gate region, a second gate region, a gap separating the first gate region and the second gate region, and a contact region electrically connecting the first gate region and the second gate region. A plurality of source/drain regions are formed in the diffusion region. The plurality of source/drain regions includes a source drain region in the gap between the first gate region and the second gate region. A plurality of pocket dopant regions are formed in the diffusion region. The plurality of pocket dopant regions includes at least one pocket dopant region in the gap between the first gate region and the second gate region.

Modular memory-like layout for finFET analog designs

Provided herein are methods for identifying individuals diagnosed with a cell proliferative disorder that will benefit from treatment with a telomerase inhibitor compound. Also provided herein are methods for treating these individuals with telomerase inhibitor compounds.

Diagnostic markers for treating cell proliferative disorders with telomerase inhibitors

A programmable delay line comprises a delay stage responsive to an analog control signal and responsive to one or more digital control signals. The delay stage generates an output signal that is delayed relative to an input signal by a delay amount. The delay amount controlled by a value of the analog control signal and one or more values of the digital control signals. A method for controlling a delay locked loop circuit comprises providing, to a programmable delay line of the delay locked loop circuit, a one or more digital signals, and providing, to the programmable delay line, an analog signal. A first portion of a delay produced by the programmable delay line corresponds to values of the one or more digital signals. A second portion of the delay produced by the programmable delay line corresponds to a value of the analog signal.

Delay locked loop

A 360 degree camera system includes a support structure, a plurality of image capture devices, a plurality of lens systems, and an image processing system. The image capture devices are positioned such that their height is greater than their width. The image processing system includes a rotation module for remapping the pixel addresses of the image data to join the captured images along their long edges.

360 degree multi-camera system

Methods of reliably quantifying telomere length in cells or tissues that have been formalin fixed and paraffin embedded (FFPE) samples by quantitative polymerase chain reaction protocol and kits for use with such various methods are provided. The methods of the present invention may be used to predetermine an individual's response to treatment with a telomerase inhibitor, a telomere damaging agent or a telomerase activator.

Telomere length measurement in formalin-fixed, paraffin embedded (FFPE) samples by quantitative PCR

Growing community of inventors

Pleasanton, CA, United States of America

Hui Wang