Intel Corporation

Hui Shi

Robert X Jin

Su Wei Lim

Ronald W Swartz

Poh Thiam Teoh

Bruce A Tennant

Hooi Kar Loo

Yick Yaw Ho

Jennifer Chin

Yueming Jiang

Athourina Gevergiz

Techniques for embedded high speed serial interface methods are described herein. The techniques provide an apparatus for link equalization including an equalization control module to determine at least a first coefficient setting and a second coefficient setting at a remote transmitter based on an algorithm. The apparatus also includes a receiver margining module to determine a first margin value to be associated with the first coefficient setting and a second margin value to be associated with the second coefficient setting. The receiver margining module is to further determine if at least the first margin value is higher than the second margin value.

Link equalization mechanism

A transmitting device to send an input signal in a channel includes an equalization system. The equalization system includes a decision subsystem to determine when adjustments need to be made based on the frequency of 0s or 1s in the input signal. The equalization system also includes an equalization subsystem to determine, by default, or by user choice, a compensation for a channel's amplitude variation due to frequency response, and to apply the compensation to the input signal and generate an equalized output signal.

Method and system for a fast serial transmit equalization scheme

Fast serial transmit equalization scheme

A system and method are used to convert a parallel datastream to a serial datastream. N number of parallel bits are input to n number of selection devices. One of the n number of selection devices is selected as an active selection device. The active selection device is directly coupled to a corresponding current source. The (n&minus;1) inactive selection devices are coupled to a current steering device. The current steering device is coupled to the corresponding (n&minus;1) inactive selection devices. The current steering device allow taking over by input data bit or latch on the previous bit if there is no input. The parallel bit is converted to a bit in the serial datastream by generating a voltage representative of a value of the serial bit utilizing a combined current from the n current sources.

Parallel to serial conversion device and method

A system and method are used to convert a parallel datastream to a serial datastream. N number of parallel bits are input to n number of selection devices. One of the n number of selection devices is selected as an active selection device. The active selection device is directly coupled to a corresponding current source. The (n&minus;1) inactive selection devices are coupled to a current steering device. The current steering device is coupled to the corresponding (n&minus;1) inactive selection devices. The current steering devices allow taking over by input data bit or latch on the previous bit if there is no input. The parallel bit is converted to a bit in the serial datastream by generating a voltage representative of a value of the serial bit utilizing a combined current from the n current sources.

(N-1)/n current reduction scheme in a n-to-one parallel-to-serial conversion

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San Jose, CA, United States of America

Hui Shi