Zte Corporation

Huawei Technologies Co., Limited

Sanechips Technology Co., Ltd.

Hui Ren

Chunyu Tian

Youming Zhang

Lea Hwang Lee

Lihuang Li

Chuangchuang Liu

Zheng Zhang

A backlight display assembly and an apparatus on which the backlight display assembly is deployed are disclosed, to effectively improve light utilization of the backlight display assembly. The backlight display assembly includes a light filter layer, a spectrum splitting layer, and a backlight layer. The light filter layer includes a plurality of light filter units, and each light filter unit includes a plurality of different light filters. The spectrum splitting layer is disposed on one side of the light filter layer, and the spectrum splitting layer and the light filter layer are spaced from each other. The spectrum splitting layer includes a micro-nano structure including a plurality of strip structures, and an arrangement direction of the plurality of strip structures is consistent with an arrangement direction of the plurality of different light filters.

Backlight display assembly and electronic device

The present disclosure discloses a method and device for data transmission between register files. The method includes that: data in a source register file are read at a Stage i of a pipeline; and the read data are transmitted to a destination register file using an idle instruction pipeline. With the method of the present disclosure, data and mask information are transmitted using an idle instruction pipeline, without addition of extra registers for data and control information buffering, thus reducing logic consumption as well as increasing utilization of an existing functional unit.

Method and device for data transmission between register files

The disclosure provides a device for implementing address buffer management of a processor, including: an assembler configured to perform operations to obtain intermediate values when the assembler encodes a set instruction for an address automatic-increment value and boundary values, and to encapsulate the intermediate values into the set instruction for the address automatic-increment value and boundary values; and a processor configured to determine, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation, so as to achieve the address buffer management. The disclosure also provides a method for implementing address buffer management of a processor, including: a processor decodes a set instruction for an address automatic-increment value and boundary values to obtain intermediate values, and determines, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation when the processor performs a load or store instruction, so as to realize the address buffer management. Through the device and the method of the disclosure, the hardware costs of the processor are reduced and design requirements of the processor's time sequence and energy efficiency are met.

Device and method for implementing address buffer management of processor

Growing community of inventors

Shenzhen, China

Hui Ren