Cadence Design Systems, Inc.

Nio Nextev Limited

Nio Co., Ltd.

Hui Qi

Xuegang Zeng

Kenneth Robert Willis

Ambrish Kant Varma

Kumar Chidhambara Keshavan

Taranjit Singh Kukal

Jie Fang

Yaping Jiang

Bradford Griffin

Rameet Pal

Bo Li

Jing Wang

Amit Kumar Sharma

Dennis Nagle

Xiaojia Deng

Chong He

Delong Cai

Zhen Mu

Disclosed are methods and systems for characterizing and analyzing an electronic system design including a parallel interface. Some methods and systems identify an electronic design including a parallel interface, determine a single circuit representation including the parallel interface from the electronic design, and analyze the parallel interface to determine waveform responses of the parallel interface by using channel analysis techniques without performing circuit simulations. Some other methods and systems are directed at performing channel analyses for a communication interface of an electronic system by concurrently applying stimuli to corresponding transmitters of a communication interface, characterizing the communication interface to perform a single simulation on the communication interface with the stimulus to determine responses at receivers of the communication interface, and determining waveform responses of the communication interface by performing operations on the responses and an input signal to the communication interface.

Method, system, and computer program product for performing channel analyses for an electronic circuit design including a parallel interface

Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include displaying, at a graphical user interface, an electronic circuit design topology environment and allowing a user to select, create, or modify an entirely single pin topology, an entirely multi-pin topology, or a combination of a single pin topology and a multi-pin topology for one or more portions of the electronic circuit design topology environment. Embodiments may also include receiving a selection of a designated portion of the electronic circuit design topology environment and generating, at the graphical user interface, a first, pin-adjustable symbol in accordance with the selected topology at the designated portion.

System and method for pin automation for topology editing

The present disclosure relates to non-linear systems associated with an electronic circuit design. Embodiments may include identifying the non-linear system associated with the electronic circuit design and determining a degree of severity of non-linearity of the non-linear system associated with the electronic circuit design. If the degree of severity is less than a predefined threshold, embodiments may further include receiving a random input pattern and deriving a single impulse response characterization, wherein the random input pattern is based upon, at least in part, an electronic circuit simulation associated with the electronic circuit design.

System and method for enhanced characterization for system identification of non-linear systems

The invention provides a bus-bar assembly, a power battery over-load protection system and method, as well as a power battery assembly, wherein the bus-bar assembly comprises a first connection arm having one or more connection ends so as to be connected to an upstream battery cell; a second connection arm having one or more connection ends so as to be connected to a downstream battery cell; and a PTC unit connected between the first connection arm and the second connection arm. The bus-bar assembly, the over-load protection system, the power battery assembly and the vehicle or the like according to the invention has better safety and stability.

Bus-bar assembly, power battery over-load protection system and method, and power battery assembly

The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include receiving, using at least one processor, an electronic design and linking a printed circuit board (PCB) block to a physical layout associated with the electronic design. Embodiments may further include receiving, at a layout environment, at least one simulation parameter and performing, using a finite difference time domain ('FDTD') simulator, a time-domain simulation, based upon, at least in part, the at least one simulation parameter.

Systems and methods for finite difference time domain simulation of an electronic design

A fully-automatic dust proof system for quick change connector of electric vehicle is provided. The fully-automatic dust proof system of the application comprises: a base provided at the quick change connector of the battery pack; a dust proof covering plate slidably installed onto the base; an electric motor fixed on the base; a power supply electrically connected with the electric motor; a control system for controlling the motor to drive the dust proof covering plate to slide; a distance sensor for monitoring relative distance between the battery pack and the electric vehicle; and a pressure sensor for monitoring whether the dust proof covering plate is in place or not.

Fully-automatic dust proof system for quick change connector of electric vehicle

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Shanghai, China

Hui Qi