Broadcom Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Avago Technologies General IP Pte, Ltd.

Hui Pan

Yuan Yao

Junhua Tan

Karim Vincent Abdelhalim

Mostafa Mohammad Hany Ali Hammad

Michael Q Le

Ichiro Fujimori

Derek Tam

Xin Wang

Jingguang Wang

Jing Wang

Joseph Aziz

Chia-Jen Hsu

Chun-Ying Chen

Kwang Young Kim

Seong-Ho Lee

Wynstan Tong

Xin Jin

Martin Weetman

Mostafa Hammad

Described herein is an apparatus including, a decoder that is configured to decode a digital control code. The digital control code corresponds to an intensity level control code of a plurality of LEDs. The apparatus includes a modulator that modulates a combination of the decoded control code and a dither signal, wherein the combined signal has a first modulation format. The apparatus also includes a converter that generates a dimming control signal by converting the first modulation format associated with the combined signal to a programmable second modulation format.

Programmable and adaptable interface for dimming light emitting diodes

Described herein is a device comprising circuitry configured to determine, based on an input signal level, one of a first mode of operation and a second mode of operation for a light-emitting-diode (LED) driver. The circuitry activates a loop-filter associated with the first mode of operation of the LED driver in response to the input signal level being below a predetermined threshold. Moreover, the circuitry activates a pulse modulator associated with the second mode of operation of the LED driver in response to the input signal level being above the predetermined threshold.

Dual mode light emitting diode (LED) driver

A scaled voltage supply to supply voltage biases to circuits in voltage zones. The scaled voltage supply includes a master voltage corresponding to a voltage drop across a master-upper rail having a voltage Vand a master-lower rail having a voltage V=0. Further, the supply includes a voltage-divider network dividing the master voltage Vinto intermediate voltages &#x3b1;V, &#x3b2;V, etc., wherein &#x3b1; and &#x3b2; are predetermined constants. These intermediate voltages scale with the master voltage and are supplied to the voltage zones using non-invasive soft rails. In one implementation the soft rails use voltage mirrors to supply the intermediate voltages to the circuits within voltage zones.

Voltage supply for supplying in zones voltages proportional to a master supply votlage using voltage mirroring

A system includes a full-duplex driver to drive signals on a load. A hybrid element connected with the full-duplex driver controls a flow of transmission and receipt of the signals. A gain control element connected with the full-duplex driver tunes a transconductance of the full-duplex driver to match an impedance of the load. The controlled gain is based on a leakage voltage value of the full-duplex driver.

Full-duplex driver with hybrid adaptation

Systems, apparatuses, and methods are provided for analog-to-digital converters (ADCs), such as successive-approximation-register (SAR) ADCs and pipelined ADCs that utilize distributed virtual-ground switching (DVS). DVS circuits and systems receive reference signal inputs that are provided to input signal buffers at the input side of the buffers via reference switches. The input signal buffers and corresponding switches are distributed into scaled replicas that each receive an analog input signal via input signal switches during a first operational phase and are connected to top plates of corresponding distributed capacitors. The bottom plates of the capacitors are sampled to provide analog input signal representations. Based on the value of the signal representations, a state machine controls each of the switches to apply reference signals to the input buffers, during a second operation phase, and to iteratively generate additional signal representations and provide a digital signal that corresponds to the analog input signal.

Distributed virtual-ground switching for SAR and pipelined ADC

A multi-bit per cycle successive approximation register (SAR) analog-to-digital converter (ADC) may sample an input signal, successively approximate the sampled signal with a shrinking sub-range containing the signal, and output coarse digital codes corresponding to the sub-range. A sub-ranging stage may continue quantization over the sub-range by sampling and interpolating between a pair of zero crossing signals that bound the sub-range. The zero crossing signals may be taken from the SAR preamp output. The sub-ranging process may be pipelined recursively in multiple stages to increase throughput and efficiency.

Pipelined interpolating sub-ranging SAR analog-to-digital converter

Aspects of rail-to-rail line drivers using differential cascode bootstrapping are described. In one embodiment, a differential line driver includes first and second differential driver output legs. The first output leg includes a first p-type cascode stack and a first n-type cascode stack, and the second output leg includes a second p-type cascode stack and a second n-type cascode stack. The differential line driver also includes a differential cascode bootstrap circuit arrangement coupled to an output of the differential line driver. More particularly, the differential cascode bootstrap circuit arrangement is coupled between the first and second differential output driver legs and the output of the differential line driver. According to aspects of the embodiments described herein, differential line drivers with overvoltage protection and rail-to-rail output swings may be achieved. Further, the differential line drivers may be generally smaller, with cascode stack transistors of reduced in size.

Rail-to-rail line driver using differential cascode bootstraping

Disclosed are various embodiments for providing a power-efficient driver architecture supporting rail-to-rail operation in full duplex mode. A driver is configured to drive a duplex signal over a transmission medium. A hybrid is configured to recover a received signal from the duplex signal. The received signal is generated by a remote transceiver. The driver is configured to drive the duplex signal based at least in part on the received signal recovered by the hybrid.

Power efficient driver architecture

A system and method for power control in a physical layer device. Energy savings during an active state can be produced through the monitoring of a received signal level by a receiver in a physical layer device. In one embodiment, based on an indication of the received signal level or other communication characteristic of the transmission medium, a control module can adjust the signal level or amplitude and/or adjust the voltage supply.

System and method for power control in a physical layer device

An output stage of a differential line driver generates a differential output signal. A common-mode component of the differential output signal is decoupled from the differential output signal using a common-mode voltage sense. The common-mode component of the differential output signal is provided to a capacitor that is coupled between the output stage and the common-mode voltage sense.

Class AB differential line drivers

Disclosed are various embodiments of a current-mode line driver that may facilitate transmitting signals to a load. The current-mode line driver may comprise a common-mode current sense element that provides a signal corresponding to the common-mode output current of the line driver. A transconductance element receives the signal from the common-mode current sense element and provides a compensating current that is based at least in part on the signal. The compensating current may reduce the common-mode output current of the line driver.

Current-mode line driver

A method and apparatus to counter effects of an offset voltage by calibrating an analog-to-digital converter (ADC). A digital calibration loop minimizes the effects of offset voltage to improve ADC accuracy as well as provide a low-power, submicron-scale ADC. A calibration circuit senses an ADC output and adjusts a variable calibration voltage to counter the effects of the offset voltage. Reduction of the offset voltage effects increases the ADC accuracy.

Digital calibration loop for an analog to digital converter

A system and method are used to allow for phase rotator control signals to be produced that rotate bits in the signals more than one step per clock cycle. This can be done through the following operation. First and second data signals that include a plurality of data bits are stored. Rotation of data bits in the first data signal and subsequently data bits in the second data signal is controlled based on a phase control signal during each clock cycle. The first and second controlled data signals are interleaved to form first and second interleaved data signals. One of the first and second interleaved data signals is selected based on a portion of the phase control signal during a second half of the clock cycle. Finally, the selected data signal is transmitted as the phase control signal.

System for shifting data bits multiple times per clock cycle

A Z/2Z ladder network includes an R/2R ladder network having capacitors coupled across series resistors within the R/2R ladder network, wherein the capacitors are sized to substantially match delays from nodes within the ladder network to an output node. The Z/2Z ladder network can be implemented within a digital to analog controller ('DAC'), including higher resolution DACs, and high data rate DACs. In higher resolution DACs, and high data rate DACs, the Z/2Z ladder network is coupled through switches to corresponding current sources. The Z/2Z ladder is optionally implemented differentially. The invention can be implemented as a Z/kZ ladder network, where k is a real number.

Delay equalized Z/2Z ladder for digital to analog conversion

Provided are a method and system for reducing glitch in a switch circuit. A system includes a current-steering switch circuit including a main differential pair switch coupled to a first tail current having a first current value. Also included is an auxiliary differential pair switch connected to the main differential pair switch. The auxiliary differential pair switch is coupled to a second tail current and configured to substantially reduce a feed-through current associated with the main differential pair switch.

Growing community of inventors

Irvine, CA, United States of America

Hui Pan