Taiwan Semiconductor Manufacturing Comp. Ltd.

Hui Ouyang

Hun-Jan Tao

Yi-Nien Su

Yi-Chen Huang

Ming-Hong Hsieh

Yen-Ming Chen

Shiang-Bau Wang

Ming-Huan Tsai

Chun-Fai Cheng

Yuan-Hung Chiu

Matt Yeh

Han-Pin Chung

Chien-Chung Fu

Chien Chung Fu

An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.

Integrated circuit device with well controlled surface proximity and method of manufacturing same

A method for fabricating an integrated device is disclosed. In an embodiment, a hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided to the hard mask layer to make the hard mask layer more resistant to a wet etch solution. Then, a patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure.

Method of fabricating gate electrode using a treated hard mask

Via hole and trench structures and fabrication methods are disclosed. The structure includes a conductive layer in a dielectric layer, and a via structure in the dielectric layer contacting a portion of a surface of the conductive layer. The via structure includes the conductive liner contacting the portion of the surface of the first conductive layer. A trench structure is formed on the via structure in the dielectric without the conductive liner layer in the trench.

Via structures and trench structures and dual damascene structures

Via hole and trench structures and fabrication methods are disclosed. The structure comprises a conductive layer in a dielectric layer, and a via hole in the dielectric layer for exposing a portion of a surface of the conductive layer. A conductive liner covers the exposed surface of the first conductive layer. A trench is formed on the via hole in the dielectric without the conductive liner layer in the trench. Dual damascene structures and fabrications methods are also disclosed. Following the fabrication methods of the via hole and trench structures, a conductive layer is further formed in the via hole and trench structures.

Via hole and trench structures and fabrication methods thereof and dual damascene structures and fabrication methods thereof

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Hsinchu, Taiwan

Hui Ouyang