United Microelectronics Corp.

3m Innovative Properties Company

Hui-Lin Wang

Jing-Yin Jhang

Chen-Yi Weng

Yu-Ping Wang

Po-Kai Hsu

Chin-Yang Hsieh

Hung-Yueh Chen

Ching-Hua Hsu

I-Ming Tseng

Yi-Hui Lee

Ying-Cheng Liu

Yi-An Shih

Si-Han Tsai

Yi-Yu Lin

Ju-Chun Fan

Che-Wei Chang

Yi-Wei Tseng

Wei Chen

Chien-Ting Lin

Yu-Tsung Lai

Chia-Chang Hsu

Pei-Chun Chang

Yi-Syun Chou

Bin-Siang Tsai

Chun-Lung Chen

Chia-Lin Lu

Fu-Yu Tsai

Kun-Ju Li

Wei-Hao Huang

Tai-Cheng Hou

Chih-Yueh Li

Kun-Chen Ho

Wei-Xin Gao

Hsi Che Cheng

Chin-Fu Lin

Kun-Yuan Liao

Jun Xie

Chang-Min Li

Rai-Min Huang

Yu-Ru Yang

Chun-Yao Yang

Dong-Ming Wu

Tzu-Chen Fu

Chun-Hsien Lin

Hung-Chan Lin

Chih-Ming Chen

Kuo-Chih Lai

Jia-Rong Wu

Ya-Huei Tsai

I-Fan Chang

Kun-I Chou

Chien-Chi Chiu

Pei Chun Chang

Ho Hsin Kun

Ya-Jyuan Hung

Ming-Chang Lu

Meng-Jun Wang

Wen-Wen Zhang

Chun-Hao Wang

Yi-Ting Liao

Bo-Yun Huang

Shun-Yu Huang

Po-kai Hsu

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and form a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

Semiconductor device and method for fabricating the same

A magnetic random access memory structure includes a first dielectric layer, a bottom electrode layer disposed on the first dielectric layer; a spin orbit coupling layer disposed on the bottom electrode layer; a magnetic tunneling junction (MTJ) element disposed on the spin orbit coupling layer; a top electrode layer disposed on the MTJ element; a protective layer surrounding the MTJ element and the top electrode layer, and the protective layer masking the spin orbit coupling layer; a mask layer surrounding the protective layer, and a spacer layer surrounding the mask layer and the protective layer.

Magnetic random access memory structure and fabrication method thereof

A method of fabricating a semiconductor device includes the steps of: providing a semiconductor structure including a memory region and a logic region. The semiconductor structure includes a first interlayer dielectric and at least one magnetoresistive random access memory (MRAM) cell disposed on the first interlayer dielectric, and the MRAM cell is disposed in the memory region; depositing a second interlayer dielectric covering the first interlayer dielectric and the at least one MRAM cell; depositing a mask layer conformally covering the second interlayer dielectric; perform a planarization process to remove the mask layer in the memory region; after the step of performing the planarization process, removing the mask layer in the logic region.

Method for fabricating semiconductor device including embedded magnetic resistance random access memory

A method for fabricating semiconductor device includes the step of forming a magnetic tunneling junction (MTJ) on a substrate, in which the MTJ includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer and the free layer includes a magnesium oxide (MgO) compound. According to an embodiment of the present invention, the free layer includes a first cap layer on the barrier layer, a spacer on the first cap layer, and a second cap layer on the spacer.

Magnetoresistive random access memory and method for fabricating the same

A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.

A magnetic memory device includes a bottom electrode layer, a magnetic tunneling junction (MTJ) stack disposed on the bottom electrode layer, a capping layer disposed on the MTJ stack, and a top electrode layer disposed on the capping layer. The top electrode layer comprises RuO.

Magnetic memory device and fabrication method thereof

A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

A magnetoresistive random access memory device includes a bottom electrode, a spin orbit torque (SOT) layer, a magnetic tunneling junction (MTJ) and a top electrode. The bottom electrode includes a first layer and a second layer connected with the first layer. A material of the first layer includes TaN, a material of the second layer includes TaN, and the following relationships are satisfied: y2/x2>1, y1/x1≥1, and y2/x2>y1/x1. The SOT layer is disposed on the bottom electrode. The MTJ is disposed on the SOT layer. The top electrode is disposed on the MTJ.

Magnetoresistive random access memory device and method for fabricating the same

A semiconductor device includes a synthetic antiferromagnetic (SAF) layer on a substrate, a barrier layer on the SAF layer, and a free layer on the barrier layer. Preferably, the SAF layer further includes a first pinned layer, a first spacer on the first pinned layer, a second pinned layer on the first spacer, a second spacer on the second pinned layer, and a reference layer on the second spacer.

A method of manufacturing a hybrid random access memory in a system-on-chip, including steps of providing a semiconductor substrate with a magnetoresistive random access memory (MRAM) region and a resistive random-access memory (ReRAM) region, forming multiple ReRAM cells in the ReRAM region on the semiconductor substrate, forming a first dielectric layer on the semiconductor substrate, wherein the ReRAM cells are in the first dielectric layer, forming multiple MRAM cells in the MRAM region on the first dielectric layer, and forming a second dielectric layer on the first dielectric layer, wherein the MRAM cells are in the second dielectric layer.

System architecture, structure and method for hybrid random access memory in a system-on-chip

A memory array includes at least one strap region, at least two sub-arrays, a plurality of staggered, dummy magnetic storage elements, and a plurality of bit line structures. The strap region includes a plurality of source line straps and a plurality of word line straps. The two sub-arrays include a plurality of staggered, active magnetic storage elements. The two sub-arrays are separated by the strap region. The staggered, dummy magnetic storage elements are disposed within the strap region. The bit line structures are disposed in the two sub-arrays, and each of the bit line structures is disposed above and directly connected with at least one of the staggered, active magnetic storage elements.

Memory array

A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.

A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to and directly contacting the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is a single layer structure made of dielectric material and an edge of the cap layer contacts the first IMD layer directly.

A magnetic memory device includes a bottom electrode layer, a magnetic tunneling junction (MTJ) stack disposed on the bottom electrode layer, a dielectric cap layer disposed on the MTJ stack, and a metal cap layer disposed on the dielectric cap layer, wherein the metal cap layer comprises a plurality of first metal layers and second metal layers alternately stacked on the dielectric cap layer.

Magnetic memory device and method for forming the same

A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

Magnetoresistive random access memory

Growing community of inventors

Taipei, Taiwan

Hui-Lin Wang