Samsung Electronics Co., Ltd.

Hui-Kap Yang

Hyung-Jin Kim

Kyung-Ryun Kim

Jang-Woo Ryu

Yoon-Na Oh

Chul-Sung Park

Woo-Seop Jeong

Soo-Hwan Kim

Young-Gu Kang

Myung-Kyoon Yim

Kyu-Chang Kang

A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.

Semiconductor memory devices, memory systems, and methods of operating semiconductor memory devices

A memory device is provided which is capable of adjusting an operation voltage, and an application processor is provided for controlling the memory device. The memory device may include: a receiving terminal for receiving a voltage control signal from an external source, the voltage control signal being for adjusting an operation voltage level according to an operation speed of the memory device; and a voltage adjustment unit for adjusting a level of an operation voltage of the memory device in response to the voltage control signal. The level of the operation voltage is adjusted before a memory operation is performed at the operation speed corresponding to the adjusted operation voltage.

Memory device capable of adjusting operation voltage and application processor for controlling the memory device

A memory device includes a memory bank, a row selection circuit and a refresh controller. The memory bank includes a plurality of memory blocks, and each memory block includes a plurality of memory cells arranged in rows and columns. The row selection circuit performs an access operation with respect to the memory bank and a hammer refresh operation with respect to a row that is physically adjacent to a row that is accessed intensively. The refresh controller controls the row selection circuit such that the hammer refresh operation is performed during a row active time for the access operation. The hammer refresh operation may be performed efficiently and performance of the memory device may be enhanced by performing the hammer refresh operation during the row active time for the access operation.

Memory device performing hammer refresh operation and memory system including the same

A row address control circuit of a semiconductor memory device including dynamic memory cells includes a test mode setting unit, an address counter and a row address generating unit. The test mode setting unit is configured to provide a test mode signal that indicates whether a test operation is performed or not, in response to a test command; the address counter is configured to generate a first address that increases gradually; and the row address generating unit is configured to selectively choose one of the first address and a second address as a refresh address based on the test mode signal, the second address being externally provided.

Row address control circuit semiconductor memory device including the same and method of controlling row address

A memory device for early stabilization and rapid increase of a power level after deep power down exit includes a deep power down exit pulse generator, a deep power down exit mode signal generator, a current driving unit, a controller and a voltage generator. The deep power down exit pulse generator generates a deep power down exit pulse signal having a predetermined pulse width in response to a deep power down command. The deep power down exit mode signal generator generates a deep power down exit mode bias signal in response to the deep power down exit pulse signal. The current driving unit generates a deep power down exit mode reference voltage in response to the deep power down exit mode bias signal and a reference signal. The controller generates an enable signal in response to the deep power down exit mode bias signal or an active command. The voltage generator compares the deep power down exit mode reference voltage to an internal power supply voltage in response to the enable signal and outputs the internal power supply voltage. The memory device previously generates the internal power supply voltage, which is used in the active mode, in a deep power down exit mode before an active command is applied to the memory device, and thus a power-up ensuring time after deep power down mode exit can be reduced.

Memory device for early stabilizing power level after deep power down mode exit

Provided are a boosted voltage detecting circuit capable of reducing the consumption of current and reducing ripple in boosted voltage during a self-refresh operation of a semiconductor memory device, and a method of controlling the same. One embodiment of the boosted voltage detecting circuit includes a feedback unit feeding back a boosted voltage, a reference voltage receiving unit receiving a reference voltage, and a detection signal generating unit comparing output voltages received from the feedback and reference voltage receiving units and generating a detection signal according to the result of comparison.

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Hwaseong-si, South Korea

Hui-Kap Yang