Taiwan Semiconductor Manufacturing Comp. Ltd.

Hui-Jen Chu

Wen-Cheng Chien

Chen-Peng Fan

A flash EPROM device includes a floating gate electrode with a top surface and sidewalls is formed on a gate oxide layer covering a semiconductor substrate. A polyoxide cap layer is formed on the top surface of the floating gate electrode. A blanket tunnel oxide layer covers the cap layer, the sidewalls of the floating gate electrode, and the exposed surfaces of the gate oxide layer. A spacer structure is formed on the surface of the tunnel oxide layer adjacent to the sidewalls of the floating gate electrode and above the gate oxide layer. A dielectric, silicon nitride inner spacer, having an annular or an L-shaped cross section, is formed on the blanket tunnel oxide layer adjacent to the sidewalls of the floating gate electrode. In the case of the L-shaped cross section inner spacer, an outer dielectric, spacer is formed over the inner dielectric, spacer. A blanket interelectrode dielectric layer covers the blanket tunnel oxide layer, and the spacer structure. A control gate electrode is formed over the interelectrode dielectric layer on one side of the floating gate electrode.

Nitride spacer technology for flash EPROM

A method of forming a spacer structure adjacent to the sidewall of a floating gate electrode with a top surface and sidewalls, the floating gate electrode being formed on a silicon oxide dielectric layer, and the silicon oxide dielectric layer being formed on the top surface of a semiconductor substrate include the following steps. Form a cap layer on the floating gate electrode, and a blanket tunnel oxide on the device. Form an inner dielectric, spacer layer over the device including the cap layer and the sidewalls thereby with conforming sidewalls, and an outer dielectric, spacer layer over the inner dielectric, spacer layer including the conforming sidewalls. Partially etch away the outer dielectric, spacer layer with a dry etch to form a outer dielectric spacer adjacent to the conforming sidewalls. Then partially etch away more of the outer dielectric, spacer layer with a wet etch to expose a portion of the conforming sidewalls of the inner dielectric, spacer layer. Finally, etch away the portion of the inner dielectric, spacer layer unprotected by the outer dielectric spacer before forming interelectrode dielectric layers and the control gate electrode.

Growing community of inventors

Kao-hsiung, Taiwan

Hui-Jen Chu