Powerchip Technology Corporation

Advanced Ion Beam Technology, Inc.

Hui-Huang Chen

Chih-Yuan Chen

Chun-Cheng Chen

Cheng-Yuan Hsu

Da Sung

Chao-Wei Lin

Jyh-Chyuan Jan

Ching-Shiang Hwang

Ching-Ching Tsai

Ting-Jyun He

Tai-Liang Hsiung

Sheng-Fu Yang

Jian-Ming Jaw

Yun-Liang Chu

The disclosure provides a hybrid magnet structure which includes two dipole magnets assemblies arranged oppositely, and each dipole magnet assembly includes a permanent magnet, two iron cores, and a moveable magnetic field shunt element. The hybrid magnet structure is adapted to focus particle beams of different positions by applying an adjustable gradient magnetic field in the horizontal or vertical direction of the particle beam. By passing the charged particle beams through the gradient magnetic field established between the two dipole magnets, the aspect of focusing the charged particle beam is achieved. In addition, the intensity of the gradient magnetic field can be altered by adjusting the gap between the movable magnetic field shunt element and the permanent magnet, thereby controlling the particle beam size on a specific axis for different energies or masses of the charge particles.

Hybrid magnet structure

A non-volatile memory including the following elements is provided. A first conductive layer and a second conductive layer are disposed on a substrate and separated from each other. A patterned hard mask layer is disposed on the first conductive layer and exposes a sharp tip of the first conductive layer. A third conductive layer is disposed on the substrate at one side of the first conductive layer away from the second conductive layer. The third conductive layer is located on a portion of the first conductive layer and covers the sharp tip, and the third conductive layer and the first conductive layer are isolated from each other. A first doped region is disposed in the substrate below the third conductive layer. A second doped region is disposed in the substrate at one side of the second conductive layer away from the first conductive layer.

Non-volatile memory and fabricating method thereof

A novel method for manufacturing a 3-D vertical memory comprising the steps of dividing a multilayer structure composed of insulating intermediate layers and sacrificial intermediate layers into a first multilayer structure and a second multilayer structure, replacing the sacrificial intermediate layers in the multilayer structures with metal intermediate layers, and manufacturing the channel structure in two multilayer structures.

Method of manufacturing a 3-D vertical memory

A vertical capacitor-less DRAM cell is described, including: a source layer having a first conductivity type, a storage layer disposed on the source layer and having a second conductivity type, an active layer disposed on the storage layer and having the first conductivity type, a drain layer disposed on the active layer and having the second conductivity type, an address gate disposed beside the active layer and separated from the same by a first gate dielectric layer, and a storage gate disposed beside the storage layer and separated from the same by a second gate dielectric layer. The DRAM cell can be written by turning on the MOSFET formed by the storage layer, the active layer, the drain layer, the first gate dielectric layer and the address gate to inject carriers into the storage layer from the active layer.

Vertical capacitor-less DRAM cell, DRAM array and operation of the same

A dynamic random access memory cell having vertical channel transistor includes a semiconductor pillar, a drain layer, an assisted gate, a control gate, a source layer, and a capacitor. The vertical channel transistor has an active region formed by the semiconductor pillar. The drain layer is formed at the bottom of the semiconductor pillar. The assisted gate is formed beside the drain layer, and separated from the drain layer by a first gate dielectric layer. The control gate is formed beside the semiconductor pillar, and separated from the active region by a second gate dielectric layer. The source layer is formed at the top of the semiconductor pillar. The capacitor is formed to electrical connect to the source layer.

Dynamic random access memory cell and array having vertical channel transistor

Growing community of inventors

Changhua County, Taiwan

Hui-Huang Chen