Taiwan Semiconductor Manufacturing Comp. Ltd.

Hui En Yin

Ru-Gun Liu

Chih-Wei Hsu

Tsai-Sheng Gau

Wen-Chun Huang

Ming-Hui Chih

Ya-Ting Chang

Chia-Ping Chiang

Wen-Li Cheng

Ping-Chieh Wu

Tsung-Yu Wang

Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Method for coloring circuit layout and system for performing the same

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Taipei, Taiwan

Hui En Yin