Faraday Technology Corporation

National Yang Ming Chiao Tung University

Hui-Chin Yang

Chung-Ping Chung

Guan-Ying Chiou

Shun-Chieh Chang

Yi-Chi Chen

Yuan-Jung Kuo

Tzu-Min Chou

A dynamic reconfigurable heterogeneous processor architecture with load balancing and dynamic allocation method thereof is disclosed. The present invention uses a work control logic unit to detect load imbalance between different types of processors, and employs a number of dynamic reconfigurable heterogeneous processors to offload the heavier loaded processors. Hardware utilization of such design can be enhanced, and variation in computation needs among different computation phases can be better handled. To design the dynamic reconfigurable heterogeneous processors, a method of how to choose the basic building blocks and place the routing components is included. With the present invention, performance can be maximized at a minimal hardware cost. Hence the dynamic reconfigurable heterogeneous processor(s) so constructed and the load balancing and dynamic allocation method together will have the best performance at least cost.

Dynamic reconfigurable heterogeneous processor architecture with load balancing and dynamic allocation method thereof

A processor and a method for executing load operation and store operation thereof are provided. The processor includes a data cache and a store buffer. When executing a store operation, if the address of the store operation is the same as the address of an existing entry in the store buffer, the data of the store operation is merged into the existing entry. When executing a load operation, if there is a memory dependency between an existing entry in the store buffer and the load operation, and the existing entry includes the complete data required by the load operation, the complete data is provided by the existing entry alone. If the existing entry does not include the complete data, the complete data is generated by assembling the existing entry and a corresponding entry in the data cache.

Processor and method for executing load operation thereof

A method for recovering global history shift register (GHSR) and return address stack (RAS) is provided, which is applicable to an instruction pipeline of a processor and includes the following steps. First, provide a branch recovery table (BRT) and a backup stack. Whenever a branch instruction enters a predetermined stage of the instruction pipeline, add a record in the BRT according to the branch instruction. Whenever a return address is popped from the RAS of the instruction pipeline, push the return address into the backup stack. When flushing the instruction pipeline, determine a removal range of the BRT according to the condition which triggers the pipeline flush. Recover the RAS according to the records in the removal range and the backup stack. Remove all records in the removal range. Recover the GHSR of the instruction pipeline according to the removed records.

Processor and method for recovering global history shift register and return address stack thereof by determining a removal range of a branch recovery table

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Hsinchu, Taiwan

Hui-Chin Yang