Sige Semiconductor, Inc.

Gan Systems Inc.

Hugues Lafontaine

John Roberts

Michel Maurice Dion

Derek C Houghton

An integrated gate protection device P for a GaN power transistor Dprovides negative ESD spike protection. Protection device P comprises a smaller gate width wenhancement mode GaN transistor Pm. The source of Pm is connected to its gate, the drain of Pm is connected to the gate input of D, and the source of Pm is connected to the intrinsic source of D. When the gate input voltage is taken negative below the threshold voltage for reverse conduction, Pm conducts and quenches negative voltage spikes. When device P comprises a plurality of GaN protection transistors Pto Pn, connected in series, it turns on when the gate input voltage applied to the drain of Pgoes negative by more than the sum of the threshold voltages of Pto Pn. The combined gate width of Pto Pn is selected to limit the gate voltage excursion of D

Gate input protection for devices and systems comprising high power E-mode GaN transistors

This invention provides a method of depositing high-quality Si or SiGe epitaxial layers on SiGe substrates. By first depositing a thin Si seed layer on the SiGe substrate, the quality of the seed layer and of the subsequently deposited layers is greatly improved over what is obtained from depositing SiGe directly onto the SiGe substrate. Indeed, whereas the RMS surface roughness of the deposition of SiGe directly on SiGe, as measured by atomic-force microscopy (AFM), was 3&#x2013;4 nm, it was more than an order of magnitude better when a thin Si seed layer was employed. This work was performed on an ultra-high-vacuum chemical vapor deposition (UHV/CVD) system; however, the same method would apply to other deposition systems such as atmospheric-pressure, low-pressure and rapid-thermal CVD.

Method of depositing high-quality SiGe on SiGe substrates

A method of producing a bipolar transistor includes the step of providing a sacrificial mesa over a layer of SiGe in order to prevent a polysilicon covering layer from forming over a predetermined region of the SiGe layer forming the transistor base. After an etching process removes the sacrificial mesa and the SiGe layer is exposed, an oppositely doped material is applied over top of the SiGe layer to form an emitter. This makes it possible to realize a thin layer of silicon germanium to serve as the transistor base. This method prevents the base layer SiGe from being affected, as it otherwise would be using a conventional double-poly process.

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Ottawa, Canada

Hugues Lafontaine