Intel Corporation

Hiel Corporation

Hugues Labbe

Prasoonkumar Surti

Tomer Bar-On

Abhishek R Appu

Joydeep Ray

Atsuo Kuwahara

Ankur N Shah

John G Gierach

Kai Xiao

Gabor Liktor

Deepak Shashidhar Vembar

Andrew T Lauritzen

Elmoustapha Ould-Ahmed-Vall

Karthik Vaidyanathan

Adam T Lake

Jonathan Kennedy

Michael Apodaca

Sameer Kp

Altug Koker

Murali Ramadoss

Balaji Vembu

Travis T Schluessler

Chandrasekaran Sakthivel

Brent E Insko

Radhakrishnan Venkataraman

Anupreet S Kalra

Nikos Kaburlasos

Jacek Kwiatkowski

Scott R Janus

Abhishek Venkatesh

Jill MacDonald Boyce

John H Feit

Subramaniam M Maiyuran

Vasanth Ranganathan

Guei-Yuan Lueh

David M Puffer

Carsten Benthin

Jeffery S Boles

Stanley J Baran

James M Holland

Gokcen Cilingir

Barnan Das

Jong Dae Oh

David M Cimini

Srikanth Potluri

Varghese George

Carl S Marshall

Vallabhajosyula S Somayazulu

Narayan Biswal

Selvakumar Panneer

Karthik Veeramani

Mike MacPherson

Philip R Laws

Archie Sharma

Mayuresh M Varerkar

Johannes Guenther

Zhijun Lei

Sherine Abdelhak

Zhengmin Li

Jeffrey Tripp

Darrel K Palke

Jason Daniel Tanner

Wenyin Fu

Bhushan M Borole

Nilesh V Shah

Slawomir Grajewski

Tzach Ashkenazi

Maria Bortman

Itay Kaufman

Jonathan Distler

Atul Divekar

Jason Ross

Yi-Jen Chiu

Qian Xu

Peter L Doyle

Devan Burke

Sang-hee Lee

Sameer K P

Maruthi Sandeep Maddipatla

Jeffrey S Boles

David Puffer

Phillip R Laws

In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

Engine to enable high speed context switching via on-die storage

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a low precision compute engine. The system may further include a wearable display housing the second graphics engine. Other embodiments are disclosed and claimed.

Graphics system with additional context

Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.

Topology shader technology

Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

Controlling coarse pixel size from a stencil buffer

One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.

Graphics architecture including a neural network pipeline

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

Motion biased foveated renderer

An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. The resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. Other embodiments are disclosed and claimed.

Graphics anti-aliasing resolve with stencil mask

An embodiment of a graphics apparatus may include a focus identifier to identify a focus area, and a color compressor to selectively compress color data based on the identified focus area. Another embodiment of a graphics apparatus may include a motion detector to detect motion of a real object, a motion predictor to predict a motion of the real object, and an object placer to place a virtual object relative to the real object based on the predicted motion of the real object. Another embodiment of a graphics apparatus may include a frame divider to divide a frame into viewports, a viewport prioritizer to prioritize the viewports, a renderer to render a viewport of the frame in order in accordance with the viewport priorities, and a viewport transmitter to transmit a completed rendered viewport. Other embodiments are disclosed and claimed.

Predictive viewport renderer and foveated color compressor

One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.

Growing community of inventors

Folsom, CA, United States of America

Hugues Labbe