Koninklijke Philips Corporation N.v.

Nxp B.v.

Trident Microsystems (far East) Ltd.

Hugues De Perthuis

Eric Desmicht

Thierry Nouvet

St&eacute;phane Mutz

Stéphane Mutz

Thierry Gourbilleau

The present disclosure describes methods of encrypting and decrypting blocks of data stored in computer readable memory for a device using a block cipher with a nonce. In particular, methods of encrypting and decrypting blocks of data where the value of the nonce is based on previous execution instructions of a program executed by the device for a previously executed block are described. Embodiments disclosed include a method of encrypting blocks of data bits stored in computer readable memory for a device using a block cipher with a nonce and a key, the method comprising for each block of data: generating a value of the nonce based on previous execution instructions of a program executed by the device for a previously executed block of data; and encrypting the block of data with the nonce and key using the block cipher.

Nonce generation for encryption and decryption

An execution flow protection module () for a microcontroller () with a memory () and a microprocessor () is described. The module () is configured to monitor the memory () access of the microcontroller () to identify instructions fetched by the microcontroller () from the memory () for execution by the microprocessor (). The module () comprises an instruction decoder unit () for determining a program counter value associated with the execution flow of the instructions fetched by the microcontroller (); a program counter predictor unit () for predicting the program counter value of the next fetched instruction; and an interrupt module () for responding if the next instruction fetched by the microcontroller does not match the predicted program counter value.

Execution flow protection in microcontrollers

A program (MC), which can be executed by a programmable circuit, is protected in the following manner. An instruction block (IB) is provided on the basis of at least a portion (MC-P) of the program. A protective code (DS) is generated that has a predefined relationship with the instruction block (IB). The instruction block (IB) is analyzed (ANL) so as to identify free ranges (FI) within the instruction block that are neutral with respect to an execution of the instruction block. The free ranges comprise at least one of the following types: bit ranges and value ranges. The free ranges that have been identified are used for embedding (SEB) the protective code (DS) within the instruction block (IB).

Software protection

A functional unit of a device is associated with a secret. Data stored in a memory location of the device is encrypted using the secret. The memory location of the device is accessible to other functional units; but without knowledge of the secret, the stored encrypted data is useless. The sharing of the secret creates a secure path between memory locations and functional units of the device while maintaining a unitary memory architecture. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Establishing a secure memory path in a unitary memory architecture

The present invention relates to a video processing device for processing data corresponding to a sequence of pictures according to a predictive block-based encoding technique. Said device comprises a processing unit () including a reconstruction circuit () for reconstructing pictures from decoded data and an external memory () for storing reference pictures delivered by the reconstruction circuit. The processing unit further comprises a memory controller () for controlling data exchange between the processing unit and the external memory, a cache memory () for temporarily storing data corresponding to a prediction area, said data being read out from the external memory via the memory controller, and a motion compensation circuit () for delivering motion compensated data to the reconstruction circuit on the basis of the prediction area read out from the cache memory.

Video processing device with low memory bandwidth requirements

The invention relates to a functional system comprising a set of functions (F, F') which are to access a collective resource (RSRC), the system including an interface (INT) arranged to implement an access scheme (AS) including at least one state (I) defined by an order of priority for an arbitration according to which the functions (F, F&#x2032;) can access the collective resource (RSRC), the state (I) being characterized in that, for at least one set of at least two functions (F), the access possibilities in read mode (F_R) and the access possibilities in write mode (F_W) have different priority levels, the access possibilities in read mode having consecutive priority levels higher than the priority levels of the access possibilities in write mode.

Access to a collective resource in which low priority functions are grouped, read accesses of the group being given higher priority than write accesses of the group

The invention relates to a method of detecting a watermark W, formed by a set of coefficients, in an information signal S, said watermark W and said information signal S being configured in the form of matrices SM M*M. The coefficients of the Fourier transform matrix of the matrix of the signal TSM and the coefficients of the Fourier transform matrix of the watermark matrix TWM are used in a calculation step CAL of the inverse transform matrix of the multiplication ITM of the transform matrix of the signal TSM and of the transform matrix of the watermark TWM, said calculation CAL being produced in sequences which each result in obtaining I columns of the inverse transform matrix of the multiplication, where M is a multiple of I and different from I. Said I columns are stored in a memory called internal memory and the detection step DET of the watermark is achieved with each sequence by detection of peaks of each set of the I columns while said I columns are present in the internal memory. The invention permits the use of a small-size internal memory.

Optimized detection of a watermark in an information signal

Access of multiple data processing circuits to a common memory having several banks is managed, the memory being connected to one or several circuits for processing ordinary data and to a circuit for processing priority data. A method of managing access includes producing an access demand of a circuit for processing ordinary data to a bank of the memory, starting the realization of the demanded access, subsequently producing an access demand of the circuit for processing priority data to another bank of the memory, preparing, during the realization of the access demanded by the ordinary data processing circuits, the other bank of the memory, and interrupting the access in the course of realization as soon as said preparation is completed.

Access to a common memory in which a priority access to a non-active bank is prepared during a non-priority access to a different bank

Access by a function to a collective resource is controlled by requiring that the function waits for a minimum number of clock cycles CLK called latency [LAT] between two successive accesses of the function. The function is further required to wait a number of cycles called penalty [PEN] which is higher than the latency between two successive accesses when a given number of successive accesses separated in time by at least the value of the latency has taken place beforehand. Registers [REG, REG] are decremented (or incremented) with each clock cycle and incremented (or decremented) with each access of the function to the collective resource. Tests [T, T, T] are made with the contents of the registers to authorize [GRT] the access to the collective resource.

Dynamic access control of a function to a collective resource

A processing of data in cooperation with a memory (MEM), for example an MPEG decoding, has the following characteristic features. A processor (P) generates a logic request (LRQ). The logic request (LRQ) defines at least one characteristic (CAR) common to a group of data (GRP). An addressing circuit (AGA) generates a physical request (PRQ) on the basis of the logic request (LRQ). The physical request (PRQ) defines memory (MEM) addresses (A) relating to the group of data (GRP). A memory interface (INT) effects a transfer (TRNSFR) of the group of data (GRP) between the memory (MEM) and the processor (P) on the basis of the physical request (PRQ). Thus, the processor need not know how and where the data to be processed or having been processed are stored in the memory. This facilitates the design of a data processing device and, particularly, a family of such devices.

Data processing device for use in cooperation with a memory

A data processing arrangement comprises a plurality of processors and a memory interface via which the processors can access a collective memory. The memory interface comprises an interface memory (SRAM) for temporarily storing data belonging to different processors. The memory interface also comprises a control circuit for controlling the interface memory in such a manner that it forms a FIFO memory for each of the different processors. This makes to possible to realize implementations at a comparatively low cost in comparison with a memory interface comprising a separate FIFO memory for each processor.

Arrangement with a plurality of processors having an interface for a collective memory

A data processing arrangement comprises a plurality of processors. These processors share a collective memory. The arrangement comprises private buses. A private bus enables data communication exclusively between a processor and the collective memory. A memory interface provides access to the collective memory in data bursts while it produces substantially steady data streams on the private buses.

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Garcelles, France

Hugues De Perthuis