Inphi Corporation

Clariphy Communications, Inc.

Fundacion Tarpuy

Hugo Santiago Carrer

Mario Rafael Hueda

Diego Ernesto Crivelli

Oscar Ernesto Agazzi

Norman L Swenson

Martin Ignacio Del Barco

Alfredo Javier Taddei

Mauro Marcelo Bruni

Federico Nicolas Paredes

Elvio Adrian Serrano

Carl Grace

Vadim Gutnik

Paul Voois

Ramiro Rogelio Lopez

Jorge Manuel Finochietto

German Cesar Augusto Luna

Seyedmohammadreza Motaghiannezam

Martin Serra

Damian Alfonso Morero

Matias German Schnidrig

Martin Carlos Asinari

Facundo Abel Alcides Ramos

Pablo Gianni

Ariel Pola

Ramiro Matteoda

Pablo Gustavo Quiroga

Roman Antonio Arenas

Alejandro Javier Schwoykoski

Mario Alejandro Castrillon

Shih Cheng Wang

German C Luna

Adrián Ulises Morales

Geoffrey O Hatcher

Jeffrey Zachan

Michael Yeo

Andre Chartrand

María Laura Ferster

Thomas A Lindsay

Jinwoo Cho

Daniel A Tauber

Ulises Morales

Laura Maria Ferster

Cesar Sanchez Peñak

Alejandro Castrillon

Maria Laura Ferster

A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

High-speed receiver architecture

A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.

Timing recovery for optical coherent receivers in the presence of polarization mode dispersion

A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Coherent transceiver architecture

A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

A receiver for fiber optic communications.

High-speed optical communications system

A transceiver for fiber optic communications. The transceiver can include a transmitter module having a transmitter host interface configured to receive an input host signal; a transmitter framer configured to frame the input host signal and to generate a framed host signal; and a transmitter coder configured to encode the framed host signal to generate an encoded host signal for transmission over a communication channel. The transceiver can also include a receiver module having a bulk chromatic dispersion, fiber length estimation, and coarse carrier recovery circuit configured to equalize a digital input ingress signal to generate an equalized ingress signal; a receiver framer configured to frame the equalized ingress signal to generate a framed ingress signal; and a receiver host interface configured to output the framed ingress signal. The receiver host interface is compatible with a framing protocol of the receiver framer.

Single-chip transceiver with electronic dispersion compensation for coherent optical channels

A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

A transceiver for fiber optic communications.

Growing community of inventors

Mendiolaza, Argentina

Hugo Santiago Carrer