Bell Telephone Laboratories

At&t Bell Laboratories

Hugo J Beuscher

Maurice N Ransom

John R Williams

Harry L Bosco

Robert B Walford

John H Davis

Allen H Huizinga

A time division switching system having distributed control processors is disclosed. The distributed processors exchange control messages and cooperate in the completion of talking paths between subscribers. Each control message includes an address portion defining the destination for the control message and is transmitted to a time-shared space division switch on the same time multiplex lines that speech representations are transmitted. Control messages are routed by the time-shared space division switch to a control distribution unit where the address portion is interpreted. When the address portion defines a distributed processor which controls the time-shared space division switch, the control distribution unit transmits the associated control message directly to that processor. Alternatively, when the address portion defines one of the other distributed processors the control distribution unit transmits the associated control message to the defined processor via the time-shared space division switch. Additionally, each control message can comprise an intervention portion and an arrangement is associated with each distributed processor which responds to the intervention portions by altering the functions performed by an associated distributed processor.

Communication arrangements for distributed control systems

A time division switching system which includes a central control, two time-multiplexed switching units each having a control distribution unit associated therewith and a plurality of interface modules each including a selected active control unit. Data words representing subscriber-generated information are conveyed between interface modules by a selected one of the time-multiplexed switching units designated as active. The active time-multiplexed switching unit also conveys control messages between each of the interface modules and the control distribution unit associated with the active time-multiplexed switching unit. However, the time-multiplexed switching unit designated as standby is also used to convey control messages between each of the interface modules and its associated control distribution unit. Each of the control distribution units routes received control messages to the interface modules via its associated time-multiplexed switching unit or to the central control. The central control directs system operation by transmitting and receiving control messages via the time-multiplexed switching units and their associated control distribution units.

Telephone switching control arrangement

A time division switching system having distributed control processors is disclosed. The distributed processors exchange control messages and cooperate in the completion of talking paths between subscribers. Each control message includes an address portion defining the destination for the control message and is transmitted to a time-shared space division switch on the same time multiplex lines that speech representations are transmitted. Control messages are routed by the time-shared space division switch to a control distribution unit where the address portion is interpreted. When the address portion defines a distributed processor which controls the time-shared space division switch, the control distribution unit transmits the associated control message directly to that processor. Alternatively, when the address portion defines one of the other distributed processors the control distribution unit transmits the associated control message to the defined processor via the time-shared space division switch.

Control information communication arrangement for a time division

An arrangement for correcting errors in words read from a memory due to a bit in a word location of the memory being stuck in one of the two binary states, 0 or 1. The arrangement is used in cooperation with parity error detection arrangements which utilize more than one parity bit per word. Upon detection of a single parity failure in a word read from a selected word location in memory the complement of the data word which is indicated to contain a parity failure is placed in the selected word location; the memory is read at the selected word location and the data so obtained is placed back into the selected word location of the memory. After this step the data in the selected word location of memory comprises the complement of the correct data word and the parity bits are all the complement of the correct parity for that data word. The correct data word for use by the processor is thus generated by complementing this later received data. On subsequent reading of the memory at a previously failed location the corrected word in the location is recognized as such by a failure of all of the parity bits. A word in which all of the parity bits fail is automatically complemented and the result is utilized in the data processor.

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Glen Ellyn, IL, United States of America

Hugo J Beuscher