Imec

Imec Vzw

Interuniversitair Microelektronica Centrum (imec)

Other

Sait Systems

Siemens Aktiengesellschaft

Interuniversitair Micorelektronica Centrum (imec, Vzw)

Imec Co., Ltd.

Hugo De Man

Francky Catthoor

Ivo Bolsens

Jan Vanhoof

Carl Van Himbeeck

Lieven Philips

Bert Gyselinckx

Maryse Wouters

Veerle Derudder

Rik De Wulf

Sven Wuytack

Bill Lin

Miguel Miranda

Milton Hiroki Sawasaki

Chantal Ykman-Couvreur

Gauthier Lafruit

Diederik Verkest

Jan Cornelis

Karl Van Rompaey

Koen Danckaert

Eddy De Greef

Jan Bormans

Stefan Janssens

Jean-Philippe Diguet

Chidamber Kulkarni

Frank Franssen

Michael Van Swaaij

Hans Samsom

Lode Nachtergaele

Martin Janssen

Florin Balasa

One aspect of the invention includes a method of address expression optimization of source-level code. The source-level code describes the functionality of an application to be executed on a digital device. The method comprises first inputting first source-level code that describes the functionality of the application into optimization system. The optimization system then transforms the first source-level into a second source level that has fewer nonlinear operations than the first source-level code.

System and method for optimizing source code

The programmable modem for digital data of the present invention provides a highly programmable, digital modem implemented in an integrated circuit which can be customized to specific applications. The programmable modem uses spread spectrum techniques and is specifically programmable to alter the parameters of the modem to improve performance. The present invention also provides a systematic method and development kit to provide rapid customization of a modem for a particular application or for rapid specification of a high-performance application specific integrated circuit mode.

Programmable modem apparatus for transmitting and receiving digital data, design method and use method for the modem

A formalized method for part of the design decisions, related to memory, involved while designing an essentially digital device is presented. The method shows how to traverse through and how to limit the search space being examined while solving these memory related design decisions. The method focuses on power consumption of said essentially digital device. A method for determining an optimized memory organization of an essentially digital device, wherein data reuse possibilities are explored, is described.

Method for determining an optimized memory organization of a digital device

A system and method for determining optimized scheduling intervals and optimized access conflicts and for determining an optimized memory organization of an essentially digital device. The system includes an optimizer for determining an optimized scheduling of the data access instructions for a plurality of disjunct code blocks, wherein each of the code blocks include part of the data access instructions. The system performs an iterative process of successively reducing the cycle budget for selected blocks and modifying the scheduling of the selected blocks until a cumulative cycle budget for all of the blocks is met.

A formalized method and a design system are described for part of the design decisions, related to memory, involved while designing an essentially digital device. The method and system determine an optimized memory organization starting from a representation of said digital device, the representation describing the functionality of the digital device and comprising data access instructions on basic groups, which are groups of scalar signals. The method and system determine optimized scheduling intervals of said data access instructions such that execution of said functionality with the digital device is guaranteed to be within a predetermined cycle budget, the determining of the optimized scheduling intervals comprising optimizing access conflicts with respect to an evaluation criterion related to the memory cost of said digital device. An optimized memory organization is selected in accordance with the optimized scheduling intervals and the optimized access conflicts.

Method for determining a storage bandwidth optimized memory organization of an essentially digital device

A method for determining an optimized data organization in at least one first memory of an essentially digital system comprising at least the first memory and a second memory, acting as cache for the first memory, the optimized data organization being characteristic for an application, to be executed by the digital system, is presented.

Method for determining an optimized data organization

A flip-flop-based circuit architecture generates a hazard-free asynchronous signal given the SET and RESET sum-of-product (SOP) solutions to an asynchronous process. The flip-flop SET and RESET SOP solutions can be hazardous. Thus, general purpose synchronous optimization tools (which are indifferent to hazards) can be used to derive the optimal SOP solutions. A fixed layer built around the SOP cores eliminates all hazards in the circuit. In one embodiment, the architecture is optimized by eliminating an RS latch and delay lines in the SOP cores. The architecture of the present invention is guaranteed to admit any semi-modular race-free state graph representation of an asynchronous process that satisfies the n-shot requirement. The state graph representations can be examined to determine if alternate, solution-specific, simplified architectures can be employed that further decrease the final area by the elimination of flip-flops or the elimination of a timing delay.

System and method for generating a hazard-free asynchronous circuit

A programmable processing engine and a method of operating the same is described, the processing engine including a customized processor, a flexible processor and a data store commonly sharable between the two processors. The customized processor normally executes a sequence of a plurality of pre-customized routines, usually for which it has been optimized. To provide some flexibility for design changes and optimizations, a controller for monitoring the customized processor during execution of routines is provided to select one of a set of pre-customized processing interruption points and for switching context from the customized processor to the flexible processor at the interruption point. The customized processor can then be switched off and the flexible processor carries out a modified routine. By using sharable a data store, the context switch can be chosen at a time when all relevant data is in the sharable data store. This means that the flexible processor can pick up the modified processing cleanly. After the modified processing the flexible processor writes back new data into the data store and the customized processor can continue processing either where it left off or may skip a certain number of cycles as instructed by the flexible processor, before beginning processing of the new data.

Power-and speed-efficient data storage/transfer architecture models and design methodologies for programmable or reusable multi-media processors

The present invention provides a method and an apparatus for reducing the storage size required for temporary data by storage order optimization. Advantageously, the execution order optimization and the storage order optimization may be treated independently. The storage size optimization is preferably performed by determining an optimum intra-array and/or inter-array storage order based on a geometrical model. The geometrical model provides a representation of the address space occupied by an array as a function of time and allows the calculation of the window size of the occupied address/time domain of the array. Where calculations would be time-consuming, these may be shortened by making simplifying assumptions, e.g. calculation of upper and lower bounds of the window size of the occupied address/time domain of an array rather than an exact calculation. Further, heuristical simplifications are described to reduce run-times for the optimization process.

Method and apparatus for size optimization of storage units

Selected code is modeled in a polyhedral dependency graph (PDG). A placement optimizer maps each element of the PDG to an optimally placed PDG. An ordering optimizer maps the placed PDG to an optimally ordered PDG. The PDG, place PDG, and ordered PDG are combined to produce a transformation script. The transformation script is applied to the selected specification description to produce optimized selected code. Optimized selected code is combined with original code to generate a control-flow optimized code. In addition, memory directives are derived from the ordered PDG model. The memory directives and optimized code are used to generate target code for simulation or software compilation.

Control flow and memory management optimization

The present invention relates to a method and apparatus for compressing digital data, such as the digital representation of a colored image. A scanning routine is described which aims to maintain the integrity of regions of the image that the human visual system also finds important. Pixel data from the image data includes color components, e.g., intensities of three or more colors such as red, green and blue or cyan, magenta and yellow. When the color components of the pixels are represented in color space, the axes of which are the three color components with the intensities thereof as variables, it has been found experimentally, particularly for artificial or synthetic images, that significant regions in the image tend to produce clusters of points in color space. In accordance with the invention, the color space is scanned by a space filling curve to convert the coordinates in color space into a one dimensional matrix such as a histogram. If certain types of space filling curves are used, e.g., a step-wise curve such as the Peano or Hilbert fractal, the clusters of points in color space tend to produce clusters of points in the histogram. Having obtained the histogram, it is segmented into a series of bins. These bins are used to segment the original image into regions which are coded. Although the invention has been described with respect to color images and 3-D color space, the method and apparatus may be useful with other types of data and with multidimensional spaces.

Data compression method and apparatus

Programmable modem apparatus for transmitting and receiving digital

A hardware and software co-design environment and design methodology based on a data-model that allows one to specify, simulate, and synthesize heterogeneous hardware and software architectures from a heterogeneous specification. The environment and methodology of the invention allow for the interactive synthesis of hardware and software interfaces. The environment defines primitive objects to represent a specification of an essentially digital system. The primitive objects are defined by describing the specification of the system in one or more processes, each process representing a functional aspect of the system. Further, each of the processes have ports which are connected to ports of other processes with a channel. The ports structure communication between the processes.

Design environment and a design method for hardware/software co-design

Growing community of inventors

Kessel-lo, Belgium

Hugo De Man