Texas Instruments Corporation

Hugo Cheung

Lu Yuan

Terence Chiu

Ramesh Saripalli

Michael Douglas Snedeker

Johnnie F Molina

Shang-Yuan Chuang

Paul Stulik

Abdullah Yilmaz

Keith Brouse

Herbert Braisz

Paul Thomas Frost

Aditya Vighnesh Ramakanth Bommireddipalli

Anand Gupta

Rituparna Ghosh

Ruben Antonio Vasquez

Bolanle Oladapo Onodipe

Benoit Goas

Jatinder Singh

Herbet Braisz

A device includes an interface. The interface includes a plurality of pins. The interface further includes first components configured to interpret signals received at the plurality of pins according to a first protocol. The device further includes second components configured to the interpret signals received at the plurality of pins according to a second protocol. The first components are configured to disable the second components in response to a determination that the signals received at the pins correspond to the first protocol. Further, the second components are configured to disable the first components in response to a determination that the signals received at the pins correspond to the second protocol.

Protocol auto-detection

A system includes a plurality of digital-to-analog converter (DAC) channels. Each DAC channel includes a current control circuit which receives a start limit signal or an end limit signal. The current control circuit reduces an output current limit of the channel responsive to the start limit signal and increases the output current limit responsive to the end limit signal. Each channel includes a current sensor circuit adapted to measure the output current of the channel and provide a channel over-current alert signal if the output current rises above a high current limit. The system includes a controller which asserts the start limit signal if the number of channels exceeding the high current limit is greater than a maximum allowable number and asserts the end limit signal if the number of channels exceeding the high current limit is less than the maximum allowable number minus a hysteresis value.

Apparatus and method of over-current limit for multi-channel digital-to-analog converters

A current loop includes a receiver assembly and a transmitter assembly. The current loop also includes: a first conductor between the receiver assembly and the transmitter assembly; and a second conductor between the receiver assembly and the transmitter assembly to complete the current loop. The transmitter assembly includes: a Highway Addressable Remote Transducer (HART) modem; a component in communication with the HART modem via a partial set of Universal Asynchronous Receiver-Transmitter (UART) communication lines; and a break extension protocol controller coupled to or included with the HART modem and configured to support UART and non-UART communications between the HART modem and the component using the partial set of UART communication lines.

Hart-enabled device with reduced communication lines and break extension protocol

A digital demodulator for use with a Highway Addressable Remote Transducer (HART) modem is provided. Analog input signals are digitized according to a sampling clock rate to produce a discrete time signal. Filtering and edge detection allow determinations of 'mark' or 'space' data in a demodulated signal in conjunction with analyzing a detected signal period, a cycle period, count histories and/or an on/off signal period.

HART FSK digital demodulator

A method for generating a desired haptics effect is provided. A haptics effect instruction is generated by a host processor responsive to a touch screen, where the haptics effect instruction corresponds to the desired haptics effect. This haptics effect instruction is received by a haptics driver, and a haptic profile from the haptics effect instruction is generated from the haptics effect instruction. The haptic profile includes at least one of a profile word, a move word, wait/halt word, and a branch word, and a sine wave is generated from the from the haptic profile that corresponds to the desired haptics effect.

Haptics effect controller architecture and instruction set

In a data acquisition system, digitizing circuitry (A) is powered up by a control signal (ADC_CONVST), superimposing a glitch (-) on a first multiplexed and amplified signal value (V) received by the digitizing circuitry. Sampling and holding of the first multiplexed and amplified signal value occurs during a delay provided between the glitch and a beginning of a first A/D conversion of the first multiplexed and amplified signal value to allow settling of the glitch. After the first conversion begins, a second multiplexed and amplified signal value is generated. The digitizing circuitry performs the first A/D conversion during initial settling of the second multiplexed and amplified signal value and then is powered down while the second multiplexed and amplified signal value continues to settle.

Low power, high speed multi-channel data acquisition system and method

There are various methods of securing programs and data on a processor. The external address enable pin of the processor is sampled upon a power-on or reset to the processor, to determine whether or not accesses to external memory are allowed. Other changes to the external address enable pin are thereafter ignored. In addition, if it is determined that an internal memory access is occurring, the contents of such an access can be masked to prevent unauthorized viewing of the memory contents via an external memory bus. In addition, a programmable security bit may be set to disable the dumping of flash memory contents, allowing only the erasing of the flash memory.

Method and system for providing security to processors

A system for increasing the data throughput of an I2C bus including a serial clock conductor () for conducting a serial clock signal (SCK) and a serial data conductor () for conducting a serial data signal (SDA) includes clock-stretching control circuitry () coupled to the serial clock conductor () for stretching the serial clock signal (SCK) by holding the serial clock conductor () at a predetermined level to cause a master device () to stop sending the serial clock signal, and circuitry (FIG.) in the slave device () for releasing stretching of the serial clock signal (SCK) in response to a determination by the slave device () that stretching of the serial clock signal (SCK) is unnecessary.

Pipelined clock stretching circuitry and method for I2C logic system

A frequency divider (A) includes an asynchronous finite state machine (AFSM) configured as a counter () having an input coupled to an input clock signal (CLK) for producing information representative of a plurality of phase signals (F,F,F,F) each of which is a divided-down representation of the input clock signal (CLK) and each of which is phase-shifted by a predetermined amount with respect to another of the phase signals (F,F,F,F). Programmable circuitry () operates in response to both dynamic divide ratio information (DIV_RATIO) and the information representative of the plurality of phase signals (F,F,F,F) so as to generate an output clock signal (CLKOUT) that is divided down according to both the dynamic divide ratio information and the information representative of the plurality of phase signals (F,F,F,F).

AFSM circuit and method for low jitter PLL CMOS programmable divider

An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate.

Method and device for providing high data rate for a serial peripheral interface

Data speed in an IC system is increased by operating a master CPU () to pipeline a stop/start/address byte transfer instruction by setting a stop bit, setting a start bit, and storing an address byte, operating a control circuit () in response to the stop bit to automatically send a stop condition on the IC bus, operating a timing circuit () to count a predetermined delay from the stop condition, and operating the control circuit () in response to the start bit to automatically send a start condition on IC bus after the delay has elapsed. The control circuit () automatically sends the address byte on the IC bus after the start condition has been sent.

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A power-saving clock divider scheme is cost-effective, flexible, jitterless, and allows the user to keep track of time. In general, the clock divider selectively operates in a normal mode and one or more divide modes, wherein the divide modes provide a clock frequency that is a fraction of the normal clock frequency by a divisor value that is specified in a user-accessible divider register. Lower divisor values (e.g., 2, 4, 8, etc.) are preferably used for performance tuning, while large divisor values (e.g., 1024, 2048, and 4096) are preferably used for power saving.

Methods and apparatus for a system clock divider

In accordance with the present electronic design automation (EDA) for integrated circuits invention prior to synthesis, dummy elements are added to the library and an internal scan clock pin with no connections is provided. Then the design is synthesized, scan insertion is performed (defining scan chains, inserting chains), and the scan clock is connected to all flip-flops SCLK pins. Finally, the dummy elements are replaced with real gates and clock tree insertion is performed after placing the cell in a layout.

Methods and apparatus for scan insertion

A method and circuit for frequency synthesis using a low drift current controlled oscillator configured to provide a wide output frequency and high accuracy are provided. An exemplary frequency synthesis circuit is configured for programmable control of a center frequency of the current controlled oscillator to provide a wide range of output frequencies with high accuracy. In accordance with an exemplary embodiment of the present invention, an exemplary circuit comprises a phase-locked loop (PLL) circuit comprising a phase detector, a charge pump, a current controlled oscillator and a divider circuit. For programmable control of the current controlled oscillator, the PLL circuit further comprises a trim digital-to-analog converter (DAC) configured to provide a trimmed current signal for control of the current controlled oscillator. In accordance with an exemplary embodiment of the present invention, trim values for operation of the trim DAC can be suitably located within a trim register of flash memory, such as programmable flash memory within any mixed-signal device or system.

Method and circuit for frequency synthesis using a low drift current controlled oscillator with wide output frequency range

A tri-value decoder and method for decoding at least three states of an input signal are provided. An exemplary tri-value decoder and method can facilitate decoding of input signals without the use of threshold values and/or forcing a tri-state input signal to a mid-rail value for tri-state detection, and with less dependence on variations in product, process and temperature. In accordance with an exemplary embodiment, an exemplary tri-value decoder circuit comprises a switch circuit, a feedback loop and a sequence detector. An exemplary switch circuit is configured to facilitate sampling of a tri-state input signal through control by the feedback loop, with the sequence detector configured for decoding the tri-state input signal into a two-bit digital signal by detecting at least two samples of the tri-state input signal during a sampling period.

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Tucson, AZ, United States of America

Hugo Cheung