Texas Instruments Corporation

Mediatek Singapore Pte. Ltd.

Mediatek Corporation

Hugh Thomas Mair

Uming U Ko

Gordon Gammie

Alice Wang

Sumanth Katte Gururajarao

Rolf Lagerquist

Theodore Warren Houston

David Barry Scott

Franck Benjamin Dahan

Ashish Kumar Nayak

Donald George Mikan, Jr

Michael Patrick Clinton

Uming Ko

Gilles Dubost

Anshul Varma

Anand Rajagopalan

Wei Yu Chen

Xiaowei Deng

Anand Seshadri

Luan A Dang

Sylvain Dubois

Lee-Kee Yong

Steve Clynes

Ramaprasath Vilangudipitchai

Radu Avramescu

James Sangwon Song

William Douglas Wilson

Hiep V Tran

Brian King Flachs

Hao Chen

Vinod J Menezes

Chia-Wei Wang

Shyh-Horng Yang

Liming Xiu

Robert L Pitts

Palkesh Jain

Huajun Wen

Girishankar Gurumurthy

Vishnu Ravinuthula

Keerthinarayan P Heragu

Shawn Anthony Fahrenbruch

George B Jamison

Norman L Culp

Yi-Te Chiu

Wei Dong

Srinivasan Venkatraman

Cheng-Hsing Chien

Dushmantha Bandara Rajapaksha

Tam Minh Tran

Bixia Li

Sudha Thiruvengadam

Che-Wei Wu

Kin-Hooi Dia

Christophe Pierre Vatinel

Shanthi Bhagavatheeswaran

Minh Chau

Shitanshu Krishnachandra Tiwari

Sushma Honnavara-Prasad

Peter H Cumming

Sumanth K Gururjarao

Jie Gu

Philippe Royannez

Hsin-Chen Chen

Shao-Hua Huang

Donald Mikan

An integrated circuit includes a programmable delay path comprising a plurality of path delay tuners configured to receive a plurality of control signals and add to the programmable delay path an amount of cell delay and an amount of wire delay that are based on the plurality of control signals. The integrated circuit further includes a controller configured to provide the plurality of control signals to the programmable delay path, receive a signal from the programmable delay path, and compare the signal to a reference signal.

Circuit and method to measure simulation to silicon timing correlation

Described herein are improved techniques for measuring propagation delay of an integrated circuit that facilitate performing propagation delay measurements on-chip. Some embodiments relate to an integrated circuit comprising programmable oscillator circuitry with a plurality of oscillator stages that are switchable into and out of a delay path based on control signals from a controller, allowing the same programmable oscillator to generate many different oscillator signals according to the received control signals, for the controller to determine a central tendency and/or variance of propagation delay of the integrated circuit. Some embodiments relate to an integrated circuit including programmable delay paths configured to provide an amount of cell delay and an amount of wire delay based on control signals from a controller, allowing the same programmable delay path to generate signals for measuring delays due to cell and wire delays of the integrated circuit.

Clock circuits designed to compensate for supply voltage fluctuations (e.g., supply voltage droops) in central processing units (CPUs) are described. The clock circuits described herein involve reducing the clock frequency in response to a decrease to the supply voltage to a value that is approximately equal (or below) to the maximum operating frequency of the CPU at that particular supply voltage. The clock circuits described herein may include a frequency locked loops (FLL). Such FLLs may be designed to lock to a reference frequency when the supply voltage is approximately constant and to deviate from the reference frequency in response to variations in the supply voltage. In some embodiments, an FLL operates in the same supply voltage domain as the CPU.

Frequency locked loops and related circuits and methods

Various examples with respect to dual threshold clock control are described. A method involves sensing an input voltage of a processing circuit with a first mechanism and a second mechanism different from the first mechanism. The method also involves regulating a first droop of the input voltage using the first mechanism. The method further involves regulating a subsequent droop of the input voltage after the first droop using the second mechanism.

Method and apparatus of dual threshold clock control

A standard cell circuit includes a standard cell unit and a first resistive device. The standard cell unit is coupled to at least one resistor. The first resistive device is coupled to the standard cell unit and provides a first current path for a first current to flow through.

Standard cell circuitries

A dynamic power meter circuit receives a set of clock signals. The clock signals are summed by a clock sum adder, thereby generating a clock sum value. A dynamic power meter output value is generated based at least in part on the clock sum value. In one particular example, a dynamic power meter circuit receives clock signals and from them generates a clock sum model sub-value. The dynamic power meter circuit also receives event signals, and from them generates an architectural event model sub-value. A corresponding pair of clock sum model sub-value and architectural event model sub-value are then ratiometrically combined, thereby generating a dynamic power meter output value. Due to the use of both event signals and clock signals, a stream of dynamic power meter output values is generated that more closely tracks actual dynamic power of a circuit being monitored.

Dynamic power meter with improved accuracy and single cycle resolution

A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.

Fast and Autonomous mechanism for CPU OC protection

A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.

Dual-rail power equalizer

A control method for a clock signal for a CPU contained in a CMOS circuit includes: when a load current for the CMOS circuit is enabled, generating a first clock signal; in a first period, selectively gating certain cycles of the first clock signal to generate a second clock signal which has a clock rate less than a clock rate of the first clock signal; and in a second period, dithering in the gated cycles to increase the clock rate of the second clock signal to be equal to that of the first clock signal. The second clock signal is continuously input to the CMOS circuit during the first period and the second period.

Control method of clock gating for dithering in the clock signal to mitigate voltage transients

An integrated circuit structure includes a first conductive layer (MET4) including a first forked conductive structure (), an insulating layer (, ILD45) substantially disposed over the first forked conductive structure (), a plurality of conductive vias (-) through the insulating layer (ILD45) and electrically connecting with the first forked conductive structure (), and a second conductive layer (MET5) including a second forked conductive structure () substantially disposed over at least a portion of the insulating layer (ILD45) and generally perpendicular to the first forked conductive structure (), the plurality of conductive vias (-) electrically connecting with the second forked conductive structure (). Other structures, devices, and processes are also disclosed.

Conductive via structures for routing porosity and low via resistance, and processes of making

In an embodiment of the invention, a frequency divider in a phase-locked loop (PLL) circuit is provided power from the power supply that provides power to a transmission circuit. The PLL is configured to receive a first direct current (DC) reference voltage, a second DC voltage and a reference clock signal. The PLL is configured to generate a transmission clock signal. A transmission circuit is configured to receive the transmission clock signal, the second DC voltage and a data bus where the data bus includes a plurality of data bits in parallel. The transmission circuit transmits data serially.

Reduction in power supply induced jitter on a SerDes transmitter

An integrated circuit structure includes a first conductive layer (MET) including a first forked conductive structure (), an insulating layer (, ILD) substantially disposed over the first forked conductive structure (), a plurality of conductive vias (-) through the insulating layer (ILD) and electrically connecting with the first forked conductive structure (), and a second conductive layer (MET) including a second forked conductive structure () substantially disposed over at least a portion of the insulating layer (ILD) and generally perpendicular to the first forked conductive structure (), the plurality of conductive vias (-) electrically connecting with the second forked conductive structure (). Other structures, devices, and processes are also disclosed.

A device is provided that includes a chip having a processor and wake-up logic. The device also includes power management circuitry coupled to the chip. The power management circuitry selectively provides a core power supply and an input/output (I/O) power supply to the chip. Even if the power management circuitry cuts off the core power supply to the chip, the wake-up logic detects and responds to wake-up events based on power provided by the I/O power supply.

Detecting wake-up events for a chip based on an I/O power supply

Clock phases of clock signals in a dual clock tree are adjusted to compensate for variances in propagation delays of buffers in the clock tree. A first input clock and a second input clock are generated with the second input clock having a phase that is programmably shifted relative to the first input clock when the system is operating at a lowered operating voltage or different temperature, for example. The first and second input clocks are coupled to a dually clocked flip flop, each having a primary latch and a secondary latch. A composite clock signal is generated in response to the first input clock and the second input clock. For example, a first signal is latched in the primary latch in response to the composite clock signal and a second signal is latched in the secondary latch in response to the first input clock signal.

Clock phase compensation for adjusted voltage circuits

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Fairview, TX, United States of America

Hugh Thomas Mair