Hewlett-packard Company

Hugh S Wallace

Li Ching Tsai

Stuart A Bell

James S Ignowski

A dual adjust current-controlled phase locked loop is provided for allowing multiple-gain frequency acquisition of a signal. The dual adjust current-controlled phase locked loop includes a phase detector responsive to a reference signal and a synthesized signal for producing a phase error signal; a controller responsive to the phase error signal for generating coarse and fine adjust control signals; and a dual adjust current-controlled oscillator responsive to the coarse and fine adjust control signals for adjusting the oscillating frequency of the synthesized signal. The dual adjust current controlled oscillator includes a differential current controlled ring oscillator comprising a series of delay elements. Each delay element includes a high gain circuit responsive to the coarse adjust control signal and a low gain circuit responsive to the fine adjust control signal.

Dual adjust current controlled phase locked loop

A video DAC for driving video displays with reduced power dissipation is presented. This is accomplished using a dual driver circuit connected to a current mirror, the dual driver comprising a strong driver and a weak driver. The dual driver permits switching current between the video load and a dummy load. The current to the dummy load is disabled during periods when the video signal remains steady for a predetermined period of time. The dual driver, using the weak driver, disables the current to the dummy load during video blanking and synchronization periods. This scheme substantially reduces the power dissipation in the DAC.

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Ft. Collins, CO, United States of America

Hugh S Wallace