Texas Instruments Corporation

Other

Hitachi, Ltd.

Agilent Technologies, Inc.

Hugh Pryor McAdams

Scott Robert Summerfelt

Steven Craig Bartling

Juergen T Rickes

Sudhir Kumar Madan

Jeffrey E Koelling

James W Grace

Wah Kit Loh

John Anthony Rodriguez

Michael Patrick Clinton

Manish Goel

Ching-yuh Tsay

John Y Fong

Ralph H Lanham

Jose A Rodriguez-Latorre

Masayuki M Nakamura

Anand Seshadri

Jimmie D Childers

Kezhakkedath Ramunni Udayakumar

Jarrod Eliason

Danny R Cline

John Paul Campbell

Brent S Haukness

Takumi Nasu

Paulette Thurston

Paolo Tabacco

Goro Kitsukawa

Shunichi Sukegawa

Hiep V Tran

Takeshi Sakai

Takesada Akiba

Theodore Sidney Moise

William R McKee

Sung-Wei Lin

Donald J Redwine

Lionel S White, Jr

Hiroshi Otori

Katsuo Komatsuzaki

Ching-Yuh Tsay

Adin E Hyslop

Bao G Tran

Narasimhan Iyengar

Tadashi Tachibana

Bill Kraus

Jurgen Thomas Rickes

WahKit Loh

Carol A Price

Chok Y Hung

Yacoub Mustafa

Ralph H R Lanham

Changes in operating conditions, like voltage or temperature, can cause the frequency of an internal clock signal to change and negatively affect device operation. In one embodiment, a method for controlling internal clock frequency of a device includes counting a number of clock cycles of the internal clock signal relative to a current period of a system clock signal to determine a current mid-cycle count of clock cycles, wherein the internal clock signal is based on a first clock signal of a plurality of clock signals produced in the device, each having a different frequency. When the current mid-cycle count is differs from a calibrated mid-cycle count by more than a tolerable amount, a second clock signal of the plurality of clock signals is selected as the internal clock signal.

Mid-cycle adjustment of internal clock signal timing

Disclosed embodiments include a memory device having a memory array that includes a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line and a sense amplifier that includes first and second transistors arranged in a cross-coupled configuration with third and fourth transistors, the first and second transistors being of a first conductivity type and the third and fourth transistors being of a second conductivity type, a first inverter having an input coupled to a first common drain terminal of the first and third transistors and an output coupled to the first bit line, and a second inverter having an input coupled to a second common drain terminal of the second and fourth transistors and an output coupled to the second bit line.

Circuit and method for imprint reduction in FRAM memories

A method of operating a memory circuit (FIGS.A andB) is disclosed. The method includes writing true data () to a plurality of bits (B, B). A first data state () is written to a signal bit (B) indicating the true data. The true data is read and complementary data () is written to the plurality of bits. A second data state () is written to the signal bit indicating the complementary data.

A method of operating a memory circuit (FIGS.A andB) is disclosed. The method includes writing true data (01) to a plurality of bits (B, B). A first data state (0) is written to a signal bit (B) indicating the true data. The true data is read and complementary data (10) is written to the plurality of bits. A second data state (1) is written to the signal bit indicating the complementary data.

An integrated circuit including a plurality of internal clock generator circuits from which an internal clock is selected based on an external time reference. A number of cycles of internal clock signals from each of the internal clock generator circuits, or from at least one of those circuits where a frequency relationship is known, is counted relative to a system clock signal based on the external time reference. The lowest frequency internal clock signal providing at least a minimum number of cycles within the system clock period, the minimum number assuring completion of a function within a time constraint, is selected as the internal clock. Robust performance over a wide range of fabrication process parameters and operating conditions is assured.

Timing compensation using the system clock

A memory circuit to reduce active power is disclosed (FIG.). The circuit includes a sense amplifier (). A first bit line (BL) is coupled to a memory array. A second bit line (BLB) that is a complementary bit line to the first bit line is also coupled to the memory array. A first transistor (TG) is coupled between the first bit line (BL) and the sense amplifier. A second transistor (TG) is coupled between the second bit line (BLB) and the sense amplifier. A first drive circuit () is coupled between the sense amplifier and the first bit line and is operable to drive a first data signal from the sense amplifier onto the first bit line when the second transistor is off.

Single sided bit line restore for power reduction

A method of reducing leakage current in a memory circuit is disclosed (FIG.A). The method includes connecting a first supply voltage terminal (VDD) to a bulk terminal of a transistor in an active mode of operation. The method further includes detecting a low power mode (SLEEP) of operation of the transistor and disconnecting the first supply voltage terminal from the bulk terminal in response to the step of detecting.

Power reduction circuit and method

An FRAM device can comprise a sense amplifier, at least a first bitcell, a first control line, and a second control line. The first bitcell can have a bit line that connects to the sense amplifier via a first isolator and a complimentary bit line that connects to the sense amplifier via a second isolator that is different from the first isolator. The first control line can connect to and control the aforementioned first isolator. And the second control line can connect to and control the second isolator such that the second isolator is independently controlled with respect to the first isolator to facilitate testing the device.

Method and apparatus pertaining to a ferroelectric random access memory

An FRAM device can comprise a sense amplifier and at least a first bitcell. The first bitcell can have a bit line and a complimentary bit line that connects to the sense amplifier. A first precharge circuit responds to a first control signal during a test mode of operation to precharge the bit line with respect to a first voltage while a second precharge circuit responds to a second control signal (that is different from the first control signal) during the test mode of operation to precharge the complimentary bit line with respect to a test voltage that is different than the first voltage (such as, but not limited to, a test voltage of choice such as a voltage that is greater than ground but less than the first voltage).

A ferroelectric memory device includes a shunt switch configured to short both sides of the ferroelectric capacitor of the ferroelectric memory device. The shunt switch is configured therefore to remove excess charge from around the ferroelectric capacitor prior to or after reading data from the ferroelectric capacitor. By one approach, the shunt switch is connected to operate in reaction to signals from the same line that controls accessing the ferroelectric capacitor. So configured, the high performance cycle time of the ferroelectric memory device is reduced by eliminating delays used to otherwise drain excess charge from around the ferroelectric capacitor, for example by applying a precharge voltage. The shunt switch also improves reliability of the ferroelectric memory device by ensuring that excess charge does not affect the reading of the ferroelectric capacitor during a read cycle.

Ferroelectric memory with shunt device

A self-timed sense amplifier read buffer pulls down a pre-charged high global bit line, which then feeds data into a tri state write back buffer that is connected directly to the bit line. The bit line provides charge to a ferroelectric capacitor to write a logical 'one' or 'zero' while by-passing an isolator switch disposed between the sense amplifier and the ferroelectric capacitor. Because the sense amplifier uses grounded bit line sensing, the read buffer will not start pulling down the global bit line until after the sense amplifier signal amplification, which makes the timing of the control signal for this read buffer non-critical. The write-back buffer enable timing is also self-timed off of the sense amplifier. Therefore, the read data write-back to a ferroelectric memory cell is locally controlled and begins quickly after reading data from the ferroelectric memory cell, thereby allowing a quick cycle time.

Ferroelectric memory write-back

A latch circuit, such as a memory cell or a flip-flop, that is immune to single-event upset at any single node. The latch circuit includes two banks of four logic gates each. The output of each logic gate in the first bank is connected to inputs of two logic gates in the second bank, and the output of each logic gate in the second bank is connected to inputs of two logic gates in the first bank. Each logic gate includes a logic function receiving an input node and an enable signal, such as a load signal. The interconnection of the logic gates corrects single-event upset at any one of the nodes. In the memory cell arrangement, redundant data paths are used to produce two input nodes provides single-event upset immunity at those input nodes. A layout of the latch circuit that ensures that random ionization affects only a single node is also disclosed.

Latch circuit with single node single-event-upset immunity

Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.

Differential plate line screen test for ferroelectric latch circuits

Growing community of inventors

McKinney, TX, United States of America

Hugh Pryor McAdams