Intel Corporation

Digital Equipment Corporation

Cabletron Systems, Inc.

Hugh M Wilkinson, Iii

Mark B Rosenbluth

Gilbert M Wolrich

Matthew James Adiletta

Debra Bernstein

Sridhar Lakshmanamurthy

Myles Wilde

George Varghese

Nigel T Poole

Lawrence B Huston

Donald F Hooper

Yim Pun

David Romano

Raymond Ng

Robert J Kushlis

A device and method for processing a data packet at a device are described. The device receives data packets and determines available memory in one or more of local memories of a plurality of execution threads. The device stores packet information in an available one of the local memories of the execution threads.

Processing a data packet

A system and method for employing registers for data transfer in multiple hardware contexts and programming engines to facilitate high performance data processing. The system and method includes a processor that includes programming engines with registers for transferring data from one of the registers residing in an executing programming engine to a subsequent one of the registers residing in an adjacent programming engine.

Registers for data transfers

A system and method for reassembling c-frames into coherent packets are disclosed. C-frames contain segments of a data set. A micro-engine operating multiple threads copies the data set segments into assigned queues, following a thread hierarchy to keep the segments in order. The queues are stored in SRAM. The micro-engine maintains a subset of the total number of queues in local memory. If a segment belongs to a queue not in local memory, the least recently used queue is copied to SRAM, the required queue is read from SRAM, and the queue is updated with the data set segment.

Method and apparatus to process switch traffic

A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes processing a sequence of packets with a sequence of threads, with the sequence of threads spanning multiple programmable processing elements integrated within a processor, and with the programmable processing elements providing multiple threads of execution such that each of the threads acquires exclusive modification access to data shared.

Processing packet sequence using same function set pipelined multiple threads spanning over multiple processing engines and having exclusive data access

In-band flow control data may be received from a switch fabric at a first network processor. The received in-band flow control data may be transmitted to a second network processor using a flow control bus. The second network processor may determine which receive queues in the switch fabric exceed a predetermined overflow threshold based on the in-band flow control data. The second processor may transmit data to the receive queues in the switch fabric determined not to exceed the predetermined overflow threshold.

Method and apparatus to communicate flow control information in a duplex network processor system

A method of parallel hardware-based multithreaded processing is described. The method includes assigning tasks for packet processing to programming engines and establishing pipelines between programming stages, which correspond to the programming engines. The method also includes establishing contexts for the assigned tasks on the programming engines and using a software controlled cache such as a CAM to transfer data between next neighbor registers residing in the programming engines.

Context pipelines

A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing data including programming engines that support multiple contexts arranged to provide a functional pipeline by a functional pipeline control unit that passes functional data among the programming engines.

Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section

Aspects of the invention include a method of conducting a reduced length search along a search path. A node which would otherwise occur between a previous and a following node in the search path is eliminated, and information is stored as to whether, had said eliminated node been present, the search would have proceeded to the following node. During the search, a search argument is compared with the stored information, and the search effectively progresses from the previous node directly to the following node if the comparison is positive. In preferred embodiments, some nodes provide result values for the search, and a node is eliminated only if its presence would not affect the result value for the search. In another aspect, the invention features a method of conducting a two mode search of reduced length. For a first mode of the search, nodes along a search path are provided, at least some of the nodes including one or more pointers pointing to other nodes. A search argument comprising a series of search segments is provided, some values of segments of the argument corresponding to nodes along the search path, some other values of the segments relating to a second mode of the search. Indicators associated with nodes are provided, each indicator indicating the segments corresponding to the second mode. The search path is searched by processing successive search segments by inspecting the indicator associated with each node, and proceeding to the second search mode if the indicator indicates that the segment relates to the second mode.

Growing community of inventors

Newton, MA, United States of America

Hugh M Wilkinson, Iii