Sun Microsystems, Inc.

Encore Computer U.s., Inc.

Gould Computer Systems Inc.

Hugh M Humphreys

Gavin G Gibson

John D Acton

Michael D Derbish

Steven P Kent

William B DeRolf

Jack M Hardy, Jr

Steven E Schelong

Ricardo Yong

Walter T Nixon

Anil Gupta

James A Starkweather

William H Brown

A data processing system comprises a plurality of nodes and a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a memory which is partitioned into a plurality of sections, including a first section for directly sharable memory located on the printed circuit board, and a second section for block sharable memory. A local bus connects the processor, block sharable memory and printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board. The printed circuit board includes a sensor for sensing when data is transferred into the directly sharable memory, a queuing device for queuing the sense data, a serializer for serializing queued data, a transmitter for transmitting serialized data onto the serial bus to a next successive processing node, a receiver for receiving serialized data from a preceding processing node, and a deserializer for transforming received serialized data into a parallel format.

Data processing system including a shared memory resource circuit

A data processing system includes a plurality of nodes, a serial data bus interconnecting the nodes in series in a closed loop for passing address and data information, and at least one processing node. In one construction, this processing node has a processor, a printed circuit board, a memory partitioned into first and second sections and a local bus connecting the processor, a block sharable memory section of the memory, and the printed circuit board. The local bus is used for transferring data in parallel from the processor to a directly sharable memory section of the memory on the printed circuit board and for transferring data from the block sharable memory to the printed circuit board. The printed circuit board includes a sensor for sensing when data is transferred into the directly sharable memory, a queuing device for queuing the sensed data, a serializer for serializing the queued data, a transmitter for transmitting the serialized data onto the serial data bus to the next successive processing node, a receiver for receiving serialized data from next preceding processing node, and a deserializer for deserializing the received serialized data into parallel data.

Computing system having multiple nodes coupled in series in a closed loop

Multiprocessor distributed memory system and board and methods therefor

A real time data processing system consisting of a plurality of processing nodes and a write only reflective data link for transferring information containing writes only between the plurality or processing nodes. All the nodes include a bus, a processor coupled to the bus, a memory having at least two ports with one port connected to the bus and the other port connected to the data link and a sensor for sensing a write to the memory. At least one node has a VMEbus as the bus and serves as an I/O connected to one port of the memory. Further a local bus included for inputting and outputting from the memory. The local bus is connected to a third port of the memory.

Real time multiprocessor system having a write only data link connected

A synchronous communications multiplexer for connecting a plurality of synchronous communications lines to an MP (multi-purpose) bus. In its basic form, the multiplexer is capable of handling bit oriented protocols (BOP) and is capable of being upgraded to support byte-oriented protocols. The present invention supports full- or half-duplex data rates of up to 19,200 baud. Total throughput, when operating with four ports (as an example), is in the range of 76.8 kbits/sec. A special mode of operation (unisync) allows operating a single port at 56 kbits/sec., full duplex. Other capabilities include software-selection of parameters (such as baud rate) and operation in a 'transmitter queueing' mode of operation.

Synchronous communications multiplexer

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Coral Springs, FL, United States of America

Hugh M Humphreys