International Business Machines Corporation

Huei Ling

Jeffrey N Weiss

Hsieh T Hao

Howard E Sachar

Leslie C Garcia

Nany H Kollesar

Yannis J Yamour

A floating point arithmetic unit that executes a single compound instruction that produces the result A+B.times.C with A, B and C being floating point numbers. Arithmetic on the exponents of A, B and C provide a normalized result of the multiplication before the addition takes place producing a normalized result of the compound instruction. The final normalized result is identical to a result that would be obtained by executing a separate instruction for the multiply, with normalized result, followed by an add instruction with a normalized result.

Floating point unit for calculating a compound instruction A+B.times.C

Equipping a secondary data flow facility with additional capability, to emulate for certain operations the simultaneous processing of the prerequisite instruction and the dependent instruction, significantly improves simultaneous pipeline processing of inherently sequential instructions (k)-at-a-time, by eliminating delays for calculating prerequisite operands. For example, Instruction A+B=Z1 followed by Instruction Z1+C=Z2 is inherently sequential, with A+B=Z1 the prerequisite instruction and Z1+C=Z2 the dependent instruction. The specially equipped secondary data flow facility does not wait for Z1, the apparent input operand from the prerequisite instruction; it simulates Z1 instead, performing A+B+C=Z2 in parallel with A+B=Z1. All data flow facilities need not be fully equipped for all instructions; the secondary data flow facility may be generally less massive than a primary data flow facility, but is more sophisticated in a critical organ, such as the adder. The three-input adder of the secondary data flow facility emulates the result of a two-input adder of a primary data flow facility, occuring simultaneously in the two-input primary data flow facility adder, adding the third operand to the emulated result, without delay. The instruction unit decodes the instruction sequence normally to control (k)-at-a-time execution where there are no instruction interlocks or dependencies; to delay execution of dependent instructions until operands become available; and to reinstate (k)-at-a-time execution in a limited number of cases by using the additional capability of the secondary data flow facility to emulate the prerequisite operands. A control unit performs housekeeping to execute the instructions.

(k)-Instructions-at-a-time pipelined processor for parallel execution of

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Chappaqua, NY, United States of America

Huei Ling