Cadence Design Systems, Inc.

Hudson Dyele Oliveira

Raquel Lara Dos Santos Pereira

Abner Luis Panho Marciano

Adriana Cassia Rossi De Almeida Braz

Rodrigo Fonseca Rocha Soares

Guilherme Seminotti Braga

Laiz Lipiainen Santos

Breno Rodrigues Guimares

Caio Texeira Campos

Disclosed are techniques for implementing formal verification of an electronic design. These techniques identify a target property for verification in a hierarchical electronic design that has a plurality of hierarchies and perform hierarchical synthesis on a hierarchy or a portion thereof in the plurality of hierarchies while black-boxing a remaining portion of the hierarchical electronic design. Cone of influence (COI) data that is relevant to the target property may be determined at least by extracting the cone of influence data from a hierarchically synthesized hierarchy or portion of the hierarchy or the portion thereof. At least the cone of influence data may be forwarded to a formal engine that uses the cone of influence data to verify the target property.

Methods, systems, and computer program product for verifying an electronic design

Growing community of inventors

Belo Horizonte, Brazil

Hudson Dyele Oliveira