U.S. Philips Corporation

Hubertus J Den Blanken

Paulus A Van Der Plas

Reinier De Werdt

Paulus M Van Attekum

Andre Stolmeijer

A method of manufacturing a semiconductor device is set forth, comprising a silicon body (1) having a surface (4) where there are situated a number of semiconductor regions (5, 6) and field oxide regions (7). The semiconductor regions is formed, after the field oxide regions have been provided, by implantations of n-type and p-type dopants. In accordance with the invention the implantations with the n-type dopant (10, 11, 14), which are performed using an implantation mask (8) provided on the surface and comprising openings (9) at the area of a part of the semiconductor regions (5) to be formed, are combined with the implantations with the p-type dopant (12, 13, 15) which are carried out without using the implantation mask. Thus, the semiconductor regions (5, 6) are realised by means of a single implantation mask (8).

Method of manufacturing a semiconductor device comprising a silicon body

A method of manufacturing a semiconductor device, in which a first pattern of conductors (20), an isolating layer (21) and a second pattern of conductors (22) are successively provided on a surface (2) of a semiconductor body (1) adjoined by a number of isolation regions (4, 10) and a number of semiconductor regions (3). Mutual contacts are established between the two patterns (20, 22) and these contacts are located both above a semiconductor region (3) and above an adjoining isolation region (4, 10) by forming conductive pillars (44) in the first pattern (20), exposing a tip (51) of the pillars (44) after an isolating layer (50) has been provided and providing the second pattern (22) over the tip (51) of the pillars (44). Thus, a large amount is saved on the surface (2).

Method of manufacturing a semiconductor device having interconnections

A method is provided in which an implantation treatment is carried out at a high energy of implantation in a semiconductor body (1) provided with a pattern of field insulation (6a) and in which the semiconductor body is provided with a masking, comprising a comparatively thin layer (8), a second comparatively thick layer (9) of a semi-masking material and a third comparatively thin layer (10). The second layer (9) is provided with openings (12) and the first layer (8) covers at least those parts of the surface which correspond to these openings (12). The third layer (10) has openings (22) each corresponding to one of the openings (12). The material of the first layer (8) differs from that of the second layer (9) and the material of the second layer (9) differs from that of the third layer (10). Preferably, simultaneously with the second layer (9) on the front side a semiconductor layer (19) is provided on the back side (3 ) of the semiconductor body (1).

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Eindhoven, Netherlands

Hubertus J Den Blanken