International Business Machines Corporation

Globalfoundries Inc.

Lenovo (singapore) Pte. Ltd.

Hubertus Franke

Gokul Bhargava Kandiraju

Bulent Abali

Pratap Chandra Pattnaik

Chung-Sheng Li

Hartmut Penner

David Jones Craft

Davide Pasetto

Pradip Bose

John Michael Tracey

Alper Buyuktosunoglu

Hong Min

Nagui Halim

Matt Richard Hogstrom

Brad L Brech

Michael D Williams

Dinesh C Verma

Douglas Morgan Freimuth

Charles P Wright

David P Olshefski

Lisa Cranton Heller

Damian Leo Osisek

Martin Schwidefsky

Claude Basso

Jean Louis Calvignac

Giora Biran

Gustav E Sittmann, Iii

Dimitrios Pendarakis

Robert William Wisniewski

David Bruce Lindquist

Mark Edwin Giampapa

Jeffrey Alan Frey

Josyula R Rao

Harold Wade Cain, Iii

Erich Miles Nahum

Terence Patrick Purcell

Rama Krishna Govindaraju

Chih-Jen Chang

Ulrich Alfons Finkler

Mandayam Thondanur Raghunath

Douglas James Joseph

Orran Yaakov Krieger

John-David Wellman

Amit Golander

Thai Franck Le

Augusto Javier Vega

Bryan Savoye Rosenburg

Paul R Bastide

Rajiv V Joshi

Maja Vukovic

Hung Qui Le

Fabrice Jean Verplanken

Charles Ray Johns

Manish Satyapal Gupta

Kun Wang

Eren Kursun

Colin Beaton Verrilli

Bartholomew Blaner

Ravi Nair

Jinho Hwang

Christoph Raisch

Hillery C Hunter

Jose Eduardo Moreira

Balakrishna Raghavendra Iyer

Brian Mitchell Bass

Chen-Yong Cher

Guogen Zhang

Damir Anthony Jamsek

Seetharami R Seelam

James Xenidis

Nikolaos Anerousis

Mohammad Banikazemi

Jon K Kriegel

Kun Bai

Robert Matthew Senger

Renato John Recio

Hendrik F Hamann

James Allan Kahle

Matthias Klein

Makoto Ono

Yu-Cheng Hsu

Donna N Dillenberger

Jinjun Xiong

Marco Kraemer

Kattamuri Ekanadham

David R Safford

Lorraine M Herger

Yi Ge

Ashutosh Misra

You-Chin Gene Fuh

Girish Gopala Kurup

Yoonho Park

Constantin Mircea Adam

Joefon Jann

Rong Nickle Chang

Todd Alan Inglett

Alan Weger

Dan Edward Poff

Edward Charles Snible

John J Reilly

Techniques for managing and processing of configuration changes associated with a service container associated with a service mesh are presented. An application management component can determine immutable configuration data (ICD) relating to configuration change processing for the service container based on policies received from an application owner. A message processing component (MMC) of a service proxy associated with the service container can receive, via a control plane, a message associated with an untrusted entity. MMC can determine whether the message comprises a configuration change request relating to interaction between the application and the service mesh, and, if so, can determine whether to allow the service proxy to process the configuration change based on analysis of the configuration change and ICD. If ICD indicates the configuration change is not allowed, service proxy can discard the request. If ICD indicates the configuration change is allowed, service proxy can implement the configuration change.

Trusted execution environment for service mesh

Storing compressed data objects by decompressing a first data object, identifying, differences between the first and second data objects, creating a new version of the second data object according to the differences, the first data object, and a reference object, and storing the first data object and the new version of the second data object.

Object storage deduplication

Tasks of directed acyclic graphs (DAGs) may be dynamically scheduled based on a plurality of constraints and conditions, task prioritization policies, task execution estimates, and configurations of a heterogenous system. A machine learning component may be initialized to dynamically schedule the tasks of the DAGs.

Learning agent based application scheduling

An apparatus, a method, and a computer program product are provided that provide confidential computing on virtual machines by securing input/output operations between a virtual machine and a device. The method includes receiving an input/output (I/O) transaction from an I/O device requesting data stored memory from a virtual machine. The I/O transaction includes a virtual memory address and a bus device function. The method also includes associating the I/O transaction with a key slot associated with the virtual machine and retrieving, using the key slot, an encryption key used to encrypt and decrypt the data. The method further includes retrieving the data located at a physical memory address in physical memory relating to the virtual memory address of the data being requested and decrypting, during a read operation, the data using the encryption key for I/O transmission. The method also includes transmitting the decrypted data to the I/O device.

Secure communication of virtual machine encrypted memory

Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous system-on-chip and communicatively coupled to a scheduler, where the directed acyclic graph corresponds to a control flow graph of respective tasks associated with an application executed by the heterogeneous system-on-chip. The techniques further including determining, using a learning agent implementing machine learning algorithms, a rank for a respective task in the directed acyclic graph, wherein the learning agent receives as input the directed acyclic graph, constraints associated with the directed acyclic graph, and heuristics regarding previously completed tasks. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous system-on-chip according to the rank.

Heterogeneous system on a chip scheduler with learning agent

Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous SoC and communicatively coupled to a scheduler, wherein the directed acyclic graph corresponds to a control flow graph of tasks associated with an application executed by the heterogeneous SoC. The techniques further including determining a rank for a respective task in the directed acyclic graph, wherein the rank is based on a priority of the respective task and a slack in the directed acyclic graph. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous SoC according to the rank.

Heterogeneous system on a chip scheduler

In an approach to extending the lifespan of a flash-based storage device, responsive to receiving a signal from a storage device that the storage device is low on extra blocks, one or more free logical blocks that are no longer needed are released. The storage device is notified of the one or more free logical blocks that are no longer needed. Responsive to determining that the number of valid physical blocks is greater than the number of used logical blocks, the advertised capacity of the storage device is reduced.

Extending the lifespan of a flash-based storage device

Systems and methods for monitoring current anomaly are described. In an example, a device can measure first current flowing along a first liner between an instrument to an equipment. The device can measure second current flowing along a second line between the equipment to the instrument. The device can compare the measurements of the first current and the second current. The device can identify a presence of current anomaly based on the comparison of the measurements of the first and second currents. The device can, in response to the presence of the current anomaly, disconnect the instrument from the equipment.

Protection adapter for oscilloscope probes

A flash translation layer method, system, and computer program product, include performing a virtualization of a meta-flash translation layer by: instantiating a range in a NAND chip comprising the number of free blocks using a meta-FTL to create a compatible range of blocks for a type of a feature and a flash characteristic of a translation table if a number of free blocks are available in the NAND chip and instantiating a second range in the NAND chip comprising a second number of free blocks using the meta-FTL to create a second compatible range of blocks for a second type of feature and a second flash characteristic of the translation table, and dynamically programming data on the fly based on an input requirement of a request into the range and the second range.

System, method and computer program product for instantiating blocks of a solid-state disk to include different flash characteristics

Techniques for power savings in communications equipment are provided. The computer-implemented method can comprise identifying, by an electronic device operatively coupled to a processing unit, one or more connectivity requirements of one or more servers associated with a data center. The computer-implemented method can also comprise determining, by the electronic device, a defined graph that satisfies the one or more connectivity requirements. The computer-implemented method can further comprise powering down, by the electronic device, one or more elements of the data center that are not required by the defined graph; and powering up, by the device one or more nodes of the data center, which are in any state other than power up, that are required by the defined graph.

Method and apparatus for power savings in communications equipment

A computer system includes a processor, main memory, and controller. The processor includes a plurality of hardware threads configured to execute a plurality of software threads. The main memory includes a first register table configured to contain a current set of architected registers for the currently running software threads. The controller is configured to change a first number of the architected registers assigned to a given one of the software threads to a second number of architected registers when a result of monitoring current usage of the registers by the software threads indicates that the change will improve performance of the computer system. The processor includes a second register table configured to contain a subset of the architected registers and a mapping table for each software thread indicating whether the architected registers referenced by the corresponding software thread are located in the first register table or the second register table.

Dynamic update of the number of architected registers assigned to software threads using spill counts

Various embodiments are provided for managing multiport banked memory arrays in a computing system by a processor. One or more conflicts may be eliminated in a multiport banked memory array upon receiving one or more write operations, read operations, or a combination thereof according to a selected priority and access protocol.

Minimizing conflicts in multiport banked memory arrays

A method, system and computer program product for adjusting prices for goods and services offered using a computer network. In one embodiment, data relating to goods and services offered over the computer network by a number of entities using the computer network are stored in a database, communications are monitored, using the computer network, to identify an interest of a user, and this interest of the user and the data in the database are used to identify one of the entities to offer a specified product or service to the user. Information is obtained relating to a price for the specified product or service, and this information and the data in the database are used to determine an adjusted price for the specified product or service. In one embodiment, the information the user has about a price for the specified product or service is used to determine the adjusted price.

Individual online price adjustments in real time

A timbre creation method, system, and computer program product include performing a timbre analysis of a sound from an input source to generate a digital fingerprint of the sound, performing deep learning to create a patch that matches the digital fingerprint, and generating a second patch for a synthesizer which reproduces a timbre that complements the digital fingerprint based on the patch.

Timbre creation system

Techniques that facilitate hybrid memory access frequency are provided. In one example, a system stores access frequency data for storage class memory and volatile memory in a translation lookaside buffer. The access frequency data is indicative of a frequency of access to the storage class memory and the volatile memory. The system also determines whether to store data in the storage class memory or the volatile memory based on the access frequency data stored in the translation lookaside buffer.

Hybrid memory access frequency

Growing community of inventors

Cortlandt Manor, NY, United States of America

Hubertus Franke