Freescale Semiconductor,inc.

Nxp Usa, Inc.

Nxp B.v.

Stmicroelectronics S.r.l.

Hubert Martin Bode

Patrice M Parris

Weize Chen

Richard J De Souza

Andreas Laudenbach

Andreas Johann Roth

Mathieu Gauthier Lesbats

Kurt U Neugebauer

Engelbert Wittich

Alexander Hoefler

Richard J DeSouza

Stephan Lehmann

Dirk Wendel

Stefan Doll

Glenn Charles Abeln

Mauro Giacomini

Markus Regner

Rishi Bhooshan

Matej Pacha

Ilhan Hatirnaz

Xianghua Shen

Mark Lehmann

Andreas Stahl

Rafael Pena Bello

Branislav Zigmund

Florian Frank Ebert

Sebastian Raschbacher

Shilpa Gupta

Dirk Rowald

Stefan G Luft

Carlos Vazquez Goyarzu

Patrik Varecha

Bretislav Zuczek

An integrated circuit (IC) for detecting single event latch-ups (SELs) includes a plurality of wells of a memory circuit and a detection circuit. The detection circuit includes a selection circuit, a comparison circuit, and a fault collection and control management circuit. The selection circuit selects a well of the plurality of wells to sense a voltage or a current in the selected well. The well is selected based on a select signal that indicates a location of the well. The comparison circuit compares the sensed voltage or current with a predetermined threshold to generate a fault signal that may be indicative of the SEL in the selected well. The SEL may be indicative of a fault in the memory circuit. The fault collection and control management circuit determines corrective actions based on the detection of the location of the SEL.

System and method for improving safety of integrated circuits

A touch screen assembly and method of testing a capacitive touch screen are disclosed, during operation thereof in which a respectively unique drive signal is applied to each of a first plurality of lines, and each of a second plurality of lines is responsive thereto, wherein a change in a response on a one of the second plurality of lines to a one of the unique drives signals is indicative of a touch event at a cross-point of the respective ones, the method comprising: modifying an amplitude of the respective unique drive signal applied to each of the first plurality of lines; and in the event of identifying a response to each modified amplitude, on each of the second plurality of read lines, determining that the touch screen does not have a fault, and otherwise determining that the touch screen has a fault.

Test methods for capacitive touch screens, and capacitive touch screen assemblies

A memory includes a supply voltage generation circuit for providing a supply voltage to a plurality of SRAM cells of the memory during at least one mode of memory operation. The supply voltage generation circuit includes a first reference generation circuit that includes at least one SRAM cell with a replica SRAM latch. The first reference generation circuit provides a first voltage during an at least one mode of memory operation. The supply voltage generation circuit includes a second reference generation circuit that includes at least one SRAM cell with a replica SRAM latch. The second reference generation circuit provides a second voltage during the at least one mode of memory operation. The voltage generation circuit includes an output for providing a supply voltage to the plurality of cells during the at least one mode of memory operation.

Voltage generation circuit for SRAM

A System-on-Chip (SoC) includes first and second voltage supply pins configured to receive first and second supply voltages, respectively, a first supply path beginning at the first supply pin, and a supply proportion checker. The first supply path includes a first plurality of voltage supply nodes and a supply switch coupled between adjacent voltage supply nodes, wherein each node is configured to provide a corresponding internal voltage supply to a corresponding portion of the SoC. The supply proportion checker is coupled to receive the corresponding internal voltage supply from each voltage supply node, and configured to determine whether a first internal voltage supply supplied by a first supply node of the first plurality of nodes has a legitimate proportion to a second internal voltage supply supplied by a second supply node of the first plurality of nodes, wherein the legitimacy is checked using only resistors which do not require trimming.

Supply voltage proportionality monitoring in a system-on-chip (SOC)

An integrated circuit, can comprise a first power supply terminal configured to supply a first voltage, a second power supply terminal configured to supply a second voltage, a first supply monitor including a detector having a first input and a second input, and configured to provide a fault indicator based on a comparison between the first and second inputs, and switching circuitry configured to during a normal operating mode, couple a voltage derived from the first voltage to the first input and a voltage derived from the second voltage to the second input, and during a self-test mode, couple the voltage derived from the second voltage to the first input and the voltage derived from the first voltage to the second input.

Devices and methods for voltage supply monitoring

Integrated circuitry, such as a microcontroller, for controlling an electric motor includes circuitry for measuring a bi-directional current flowing within a coil of the electric motor. The current is sensed by an externally implemented current sensing element, such as a shunt resistor, to produce a differential voltage that is delivered to input pins of the microcontroller, which are protected by electrostatic discharge protection circuits. Current sources implemented within the microcontroller are coupled to the input pins, and work in concert with external resistors to shift the differential voltage so that it is maintained within an appropriate voltage operating range so that an accurate measurement of the bi-directional current can be made by the microcontroller.

Current measurement apparatus

A system for a power switch of a multiphase power converter coupled to an inductive load including a test controller, a voltage sampling circuit, a processing circuit, and a converter. A test pulse is applied to power switches of the converter to generate a test current through the inductive load, which forward biases a body diode of a power switch during a freewheel portion after the test pulse is completed. The voltage across the body diode is sampled during the freewheel portion, and the voltage samples are converted to a voltage value and a slope value. The voltage and slope values are converted to an estimated temperature value based on a characterization of the inductive load and the body diode. The conversion may be performed by a lookup table that stores an estimated temperature value for each unique combination of the voltage and slope values.

System and method of estimating temperature of a power switch of a power converter without a dedicated sensor

The disclosure relates to an integrated circuit comprising: a first voltage terminal; a second voltage terminal; and a plurality of logic cells, comprising one or more field effect transistors having a p-type channel and one or more field effect transistors having an n-type channel. The plurality of logic cells comprises a regular subset of cells and a spare subset of cells. Electrical connectors are arranged to: connect the gates of the regular subset of cells in order to provide a functional logic arrangement; connect the gates of the one or more field effect transistors having a p-type channel of the spare subset of cells to the first voltage terminal; and connect the gates of the one or more field effect transistors having an n-type channel of the spare subset of cells to the second voltage terminal.

Integrated circuit with spare cells

A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices.

Semiconductor device with non-isolated power transistor with integrated diode protection

Switching control devices and related operating methods are provided. An exemplary electronic device includes a semiconductor die, a driver arrangement on the semiconductor die to generate a switch control output signal based on an input switching command signal, and a timer arrangement on the semiconductor die and coupled to the driver arrangement to measure a time difference between a first change in the command signal and an exhibited response in the switch control signal, which can then be utilized to achieve a desired dead time.

Semiconductor devices and methods for dead time optimization by measuring gate driver response time

A method and system are provided for digitally controlling a switch mode power supply without using analog-to-digital converters by providing an SMPS output in feedback to first and second comparators along with upper and lower reference voltage thresholds to detect excursion counts at dedicated counters which identify how many times an SMPS output voltage exceeds the upper and lower reference voltage thresholds during each cycle of a fixed frequency PWM signal, where the excursion counts are evaluated with a non-linear multi-step digital control loop detection sequence to generate duty cycle adjustment instructions for controlling each duty cycle of the fixed frequency PWM signal.

Digital control algorithm using only two target voltage thresholds for generating a pulse width modulated signal driving the gate of a power MOS to implement a switch mode power supply

A SAR ADC is disclosed. The SAR ADC includes a plurality of SAR-capacitors. For each of the SAR-capacitors, a sampling-switching-block is configured to connect a first plate of the associated SAR-capacitor to either: v-ref-low, v-ref-high or an input-voltage. The SAR ADC also includes an offset-capacitor and an offset-switching-block configured to connect a first plate of the offset-capacitor to either: v-ref-low, or v-ref-high. The SAR ADC further includes a SAR machine configured to provide signals to the sampling-switching-blocks and the offset-switching-block in order to define a calibration-sampling-mode-of-operation, a calibration-conversion-mode-of-operation, a sampling-mode-of-operation and a conversion-mode-of-operation. A code converter is also includes and is configured to subtract the offset-value from the raw-digital-word in order to provide a digital-output-signal.

Analogue to digital converter

A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. At least one of the body region and the device isolating region includes a plurality of peripheral, constituent regions disposed along a lateral periphery of the active area, each peripheral, constituent region defining a non-uniform spacing between the device isolating region and the body region. The non-uniform spacing at a respective peripheral region of the plurality of peripheral, constituent regions establishes a first breakdown voltage lower than a second breakdown voltage in the conduction path.

Integrated breakdown protection

Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within a portion of the substrate contained by the isolation structure, and a resistor circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region, which is separated from the isolation structure by a portion of the semiconductor substrate having the first conductivity type. The resistor circuit is connected between the isolation structure and the body region. The resistor circuit may include one or more resistor networks and, optionally, a Schottky diode and/or one or more PN diode(s) in series and/or parallel with the resistor network(s).

Semiconductor device and driver circuit with an active device and isolation structure interconnected through a resistor circuit, and method of manufacture thereof

Protection circuits, device structures and related fabrication methods are provided. An exemplary protection circuit includes a first protection arrangement and a second protection arrangement. The first protection arrangement includes a first transistor having a first collector, a first emitter, and a first base coupled to the first emitter at a first node, and a second transistor having a second collector, a second emitter, and a second base coupled to the second emitter at a second node, the second collector being coupled to the first collector at a third node. The second protection arrangement is coupled electrically in series between the second node and a fourth node. The protection circuit further includes a first diode coupled between the third node and the fourth node.

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Haar, Germany

Hubert Martin Bode