International Business Machines Corporation

Globalfoundries Inc.

Hubert Harrer

Andreas Huber

Jochen Supper

Bruno Michel

Thomas J Brunschwiler

Harry S Barowski

Stephan Paredes

Tim Niggemeier

Jonas R Weiss

Roger F Dangel

Norbert M Meier

Erich Klink

Roland Frech

Thomas-Michael Winkel

Zhaoqing Chen

Bernd Garben

Stephen Bruce White

Martin Eckert

Thomas Strach

John William Zack

Dierk Kaller

Thaddeus Chen

Jan Elizabeth Hoffman

Susan Marie Karwoski

Joonsuk Park

Christian Jacobi

Paul William Coteus

Evan G Colgan

Daniel Mark Dreps

Patrick James Meaney

Gareth Geoffrey Hougham

Frank David Ferraiolo

John G Torok

Pak-kin Mak

Robert J Sonnelitter, Iii

Marc Henri Coq

Wiren Dale Becker

Samuel R Connor

Glenn David Gilda

Tobias Webel

Arthur J O'Neill

John Harold Magerlein

Christine Axnix

Andrew A Turner

Ulrich Weiss

Rajat Rao

Helmut H Weber

Dietmar Schmunkamp

William Frederick Shutler

Martin Bernhard Schmidt

Philip S Honsinger

Frank William Angelotti

Gary Alan Peterson

Ching-Lung L Tong

Martin Rehm

Kenneth Lee Christian

Rohan A Jones

Xiaomin Duan

Michael D Campbell

Michael Jason Cade

Katharina Scharff

Martin Kindscher

Jan Elizabeth Garrett-Hoffman

Edwin Scott Reichmann

Neil A Malek

Dermot Weldon

A method for detecting information breach in a computer system. The method comprises: detecting a radio frequency signal in an area of the computer system. A set of samples of the radio frequency signal may be input to a machine learning model. An output of the machine learning model may be received. The output indicates whether the detected radio frequency signal is anomalous. An alarm signal may be generated in case the detected radio frequency signal is predicted as an anomalous signal.

Detecting information breach in a computer system

Concurrent servicing of a first cable of a cable pair while a second cable of the cable pair remains operational improves multi-processor computer system availability and serviceability. A pair of processing chips in different processing drawers may continue operation by way of the second cable while the first cable is degraded or serviced. Upon the servicing of the first cable, the serviced cable may transition to a fully operational state with no interruptions to the operations between the processing drawers by way of the second cable. Since cable faults are typically more common than processing chip or processing drawer faults, identification of cable faults and the ability to maintain operations of the processing drawers connected therewith is increasingly important.

Cable pair concurrent servicing

Provided are embodiments including methods, systems, and computer-program products for mitigating power supply noise using one or more current supplies. In some embodiments, power is provided to an integrated circuit, wherein a first circuit is coupled to the integrated circuit over a first path. A variation of the current level of the integrated circuit may be determined. Additional power from a second circuit is provided to the integrated circuit may be provided based at least in part on the determined variation, wherein the second circuit is coupled to the integrated circuit over a second path.

Mitigating power noise using a current supply

A method is provided for determining a power noise histogram of a computer system. The computer system includes a skitter circuit with multiple skitter bins, each skitter bin of the multiple skitter bins being connected to a signal line at one or more clock cycles. The method includes: connecting each skitter bin to an individual counter circuit; and incrementing a counter when the respective skitter bin is enabled.

Power noise histogram of a computer system

A computer program product or hardware description language ('HDL') design structure in a computer-aided design system for generating a functional design model of an integrated circuitry structure including generating a functional representation of at least first and second regions of the integrated circuitry structure, generating a functional representation of an optical layer comprising optical waveguides, and generating a functional representation of a heat-conductive material for transferring heat from at least the second region through the optical layer to a heat sink.

Transferring heat through an optical layer of integrated circuitry

An integrated circuitry structure includes at least first and second regions. An optical layer includes optical waveguides. A heat-conductive material transfers heat from at least the second region through the optical layer to a heat sink.

A method in a computer-aided design system for generating a functional design model of an integrated circuitry structure including generating a functional representation of at least first and second regions of the integrated circuitry structure, generating a functional representation of an optical layer comprising optical waveguides, and generating a functional representation of a heat-conductive material for transferring heat from at least the second region through the optical layer to a heat sink.

A computer system includes a processor, and the processor includes at least one interface for communicating with an electronic component. Each of the at least one interface has a set of interface settings. The computer system further includes a memory containing machine executable instructions. Execution of the instructions causes the processor to: monitor communications traffic on the at least one interface; store, eye distribution data acquired during the monitoring of the communications traffic in a database; compare the eye distribution data to a set of predetermined criteria; and generate a set of updated interface settings if the eye distribution does not satisfy the set of predetermined criteria.

Updating interface settings for an interface

An integrated circuit coupling device includes an integrated circuit package; and an optical data transmission medium connected to the integrated circuit package, and comprising a movable coolant, adapted to remove heat from the integrated circuit package, in operation.

Integrated circuit package connected to an optical data transmission medium using a coolant

Transferring data from a first clock domain to a second clock domain, wherein the second clock domain has a fixed clock frequency, and the first clock domain has a variable clock frequency. The first clock domain and the second clock domain operate in a synchronous mode when the variable clock frequency is equal to the fixed clock frequency, and in an asynchronous mode when the variable frequency is lower than the fixed frequency. A first buffer and a second buffer are used for a data transfer from the first clock domain to the second clock domain. The second clock domain comprises a multiplexor connected to the first buffer and the second buffer. The multiplexor forwards data from the first buffer further into the second clock domain in the synchronous mode and from the second buffer into the second clock domain in the asynchronous mode.

Low latency data transfer between clock domains operated in various synchronization modes

An integrated circuit coupling device includes an integrated circuit package with N integrated circuit layers (L-L) arranged as a 3D stack; and a data transmission medium with n data transmission layers (l-l), wherein n&#x2267;1 and N&#x2267;2, and wherein the N integrated circuit layers are electrically connectable to the n data transmission layers.

Integrated circuit package connected to a data transmission medium

A technique for routing signal traces in an electronic package design includes extracting near-end and far-end crosstalk values for traces and vias from a model of the electronic package design. The extracted values are then length-normalized and the normalized values are allocated to coupling factors of a cost-function. A first bus routing for the electronic package design is performed to provide a first routed design. Length segments from the first routed design are extracted and inserted in the cost-function. Crosstalk for each bus net is accumulated using the cost-function. In response to the accumulated crosstalk being less than a determined limit, the first routed design is saved. In response to the accumulated crosstalk being greater than the determined limit, an additional bus routing for the electronic package design is performed.

Cost-function based routing techniques for reducing crosstalk in electronic package designs

A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Optimized semiconductor packaging in a three-dimensional stack

A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Thermal power plane for integrated circuits

A mechanism is provided for integrated power delivery and distribution via a heat sink. The mechanism comprises a processor layer coupled to a signaling and input/output (I/O) layer via a first set of coupling devices and a heat sink coupled to the processor layer via a second set of coupling devices. In the mechanism, the heat sink comprises a plurality of grooves on one face, where each groove provides either a path for power or a path for ground to be delivered to the processor layer. In the mechanism, the heat sink is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism and the signaling and I/O layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Heat sink integrated power delivery and distribution for integrated circuits

Growing community of inventors

Schoenaich, Germany

Hubert Harrer