Freescale Semiconductor,inc.

Nxp Usa, Inc.

Hubert Glenn Carson, Jr

Thomas Henry Luedeke

Anurag Jindal

Stefan Doll

Nikila Krishnamoorthy

Alan Joseph Carlin

Kenneth P Tumin

Joel Ray Knight

Kamel Musa Khalaf

Alex S Y Koh

Hilario Manuel Garza

Adrian Lee Carleton

A fully digital integrated circuit apparatus () and method () are provided for generating a test mode enable signal with a digital non-resettable state retention storage circuit () connected to store an authentication control pattern for authorizing test mode access to a secure circuit, a digital safety interlock gate circuit () connected to store a safety interlock gate setting that may be accessed independently from a test mode enable signal, and combinatorial logic circuitry () for generating the test mode enable signal only when the interlock safety gate setting is set to a first value and the digital non-resettable state retention storage circuit stores the authentication control code.

Method and apparatus for digital only secure test mode entry

A test pattern generation flow has a stimulus and a device under test (DUT) that operate together through a test bench. The test bench monitors and collects all the data necessary to generate a test program. This information is presented as a captured simulation that allows for ease of generating test software, as well as other simulations such as fault simulation and virtual test simulation. The complete and convenient information can be utilized to automate the development and/or easily manually develop and debug the test software.

Method for producing test patterns for testing an integrated circuit

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Austin, TX, United States of America

Hubert Glenn Carson, Jr