Hewlett-packard Development Company, L.P.

Hubert E Brinkmann

David L Matthews

Paul V Brownell

Dwight D Riley

Barry S Basile

James Xuan Dinh

Ryan A Callison

Robert C Elliott

Kenneth T Chin

Hahn Norden

Joseph Foster

Kevin G Depew

James R Reif

John M Cagle

Paul V Brownnell

Paul V Brownall

William F Doss

Embodiments of the present invention are directed to methods for virtualizing interrupt modes on behalf of interrupt-generating devices, including I/O-device controllers, so that newer interrupt-generating devices that lack older interrupt modes can be used in systems that continue to rely on older interrupt modes. In one embodiment of the present invention, a PCIe switch or PCIe-based host bridge is modified, or a new component introduced, to provide an interrupt-mode virtualizing function, or virtual interrupt-mode interface, that provides a virtual interrupt mode on behalf of interrupt-generating devices, such as I/O-device controllers, to operating systems, BIOS layers, and other components that communicate with the I/O-device controllers.

Virtual-interrupt-mode interface and method for virtualizing an interrupt mode

In one embodiment, a computer system, comprises at least one host node, at least one input/output node coupled to the host node, at least one multi-function device coupled to the input/output node via a switch, and a middle manager processor comprising logic to block an enumeration process in a host node for the multi-function devices behind the switch hierarchy, initiate an enumeration process for the multi-function devices in a manager processor separate from the host node, store a routing table for the switch hierarchy in a memory module coupled to the manager processor, and allocate, in the manager processor, endpoint device resources to the host node.

Presenting multi-function devices behind a switch hierarchy as a single function device

A blade server system and method for virtually hot plugging and virtually hot removing functions in a shared I/O environment. A management node physically hot inserts and hot removes an I/O node in the server system without a compute node being aware of the hot insert and hot removal. The management node and the compute node create and remove virtual links between the compute node and the virtual functions.

Virtual hot inserting functions in a shared I/O environment

A method and apparatus for host enumeration process. One embodiment of the method provides a bit to indicate to the host whether enumeration process should start or continue. The bit may be set when the shared resource process has been successfully completed, or the bit may be set if too much time has elapsed since the shared resource process has started, or the bit may be set if too much time has elapsed before the shared resource process is started, or the bit may be set if the shared resource process has not been performed successfully, or the bit may be set if the port is open and it is unnecessary to perform the shared resource process.

Method and apparatus for performing a host enumeration process

A method includes providing a bridge device () connected to a host computing device (--) and a peripheral device (---N,-----), the bridge device () being configured to communicatively couple the host device (--) to the peripheral device (---N,-----); and preventing execution of a hardware enumeration process () in the host device (--) until completion of a resource allocation process () in the bridge device ().

Systems and methods of communicatively coupling a host computing device and a peripheral device

Embodiments include methods, apparatus, and systems for converting resets in a shared I/O system. One embodiment includes a method that propagates a first type of reset from a host computer to a multi-function device that shares I/O operations with other hosts. The first type of reset is converted to a second type of reset to prevent the host from resetting functions bound to the other hosts at the multi-function device.

Conversion of resets sent to a shared device

A system for transforming a single root input/output virtualization (SR-IOV) function to appear as a legacy function, and a corresponding method includes a switch platform coupled between a legacy host and a SR-IOV-enabled device. The switch platform includes a processor programmed to discern configuration cycles by type and to process the configuration cycles, and one or more local registers that store data related to the configuration cycles.

System and method for transforming PCIe SR-IOV functions to appear as legacy functions

A network node within a network includes a first receive buffer, first buffer management, a second receive buffer and second buffer management. The first buffer management performs link level credit based flow control for network packets that the first buffer management places in the first receive buffer. The second buffer management performs end-to-end credit based flow control for network packets that the second buffer management receives from the first receive buffer and processes before placing data in the second receive buffer.

End-to-end flow control in a network

A system is provided comprising a fabric coupling together a plurality of computing devices, wherein the fabric transfers a stream of packets between the computing devices. Each computing device comprises a Quality of Service ('QOS') filter that monitors incoming packets to filter out packets of a maintenance type and permit transfer of packets of a transaction type.

Quality of service with control flow packet filtering

A bridge comprises an interface to a plurality of hosts, an interface to a single-ported storage drive and arbitration logic. The arbitration logic controls and permits concurrent access by the hosts to the single-ported storage drive so that the bridge need not store read or write data being received from or provided to the storage drive.

Bridge permitting access by multiple hosts to a single ported storage drive

A system includes a peripheral device and an expander having interfaces to couple to one or more peripheral devices and an expander. The expander has a storage to store entries containing routing information used to route a request received by the expander to one of the interfaces, wherein each interface is allocated to a respective set of routing information entries. Mapping logic remaps unused routing information of one of the interfaces to one or more other interfaces to expand capacity of the one or more other interfaces.

Remapping routing information entries in an expander

A drive array controller or other data handling system supports dynamic data routing across multiple data paths between a source controller and a destination controller. Each data path between the source controller and the data controller can include a cache memory. Based on detection of a cache address, the data path with the cache memory corresponding to the cache address is selected. Data transfer to a single destination controller can be alternated between different data paths based on detection of different cache addresses. Each data path can include a plurality of bus/memory interface devices and a peripheral bus such as a peripheral component interconnect (PCI) bus. As an alternative to dynamic data routing based on addressing, data routing can be based on command type.

Dynamic routing of data across multiple data paths from a source controller to a destination controller

Address translation between various peripheral bus interfaces is provided through a bus interface device. Specifically, the bus interface device translates incoming transactions from a source bus interface to a different address or location within a destination bus interface. Flexibility for communications between multiple bus interfaces having different, possibly conflicting, address spaces is ensured by allowing the internal translation registers to be dynamically reprogrammed. Reprogramming of the translation registers may occur during runtime bus operations. These registers define translation windows within which a transaction will be claimed and translated to the destination bus interface. Translation is accomplished using the translation registers to identify portions of the incoming received address which should not be translated because those portions contain the information to be communicated. At the same time, portions identifying only the location of the information are translated to identify a different location within the destination address space.

Growing community of inventors

Spring, TX, United States of America

Hubert E Brinkmann