Tsinghua University

Huawei Technologies Co., Limited

Rohm Co., Ltd.

Stmicroelectronics International N.v.

Stmicroelectronics Asia Pacific Pte Limited

Huazhong Yang

Yongpan Liu

Xueqing Li

Rong Luo

Hehe Li

Qinghang Zhao

Chen Jiang

Xiaoyang Ma

Wenjun Tang

Jialong Liu

Lei Zhang

Sapna George

Takashi Naiki

Yiming Chen

Koji Taniuchi

Shuzheng Xu

Pengjun Wang

Mufeng Zhou

Yiqun Wang

Yushen Fu

Hongtao Zhong

Xiao Sheng

Zhiyang Xing

Juejian Wu

Zewei Li

Xiyu He

Tongda Wu

Yilun Zhong

Zhongjun Wang

Weihang Long

The present disclosure relates to a sensing-memory-computing synergy device, chip and electronic device. The said device comprises: at least one sensing-memory-computing synergy cell, wherein each sensing-memory-computing synergy cell comprises K sensing elements, where the first end of each sensing element is connected to wordline, the second end of each sensing element is connected to bitline, the sensing element can sense changes in external inputs, and K is an integer greater than or equal to zero; a control module which controls the voltages of each wordline and bitline so that the sensing-memory-computing synergy cell can perform desired operations, and sense the voltage or current on bitlines to obtain the operation results. The present embodiment of the disclosure implements the sensing-memory-computing synergy cell by sensing elements, which combines sensing and in-memory computing. The sensing elements gather sensor data from external inputs, and the sensing-memory-computing synergy operation is performed by controlling the voltages on wordlines and bitlines. The present embodiment of the disclosure enables the in-situ sensing, memory and computing functions in a device with decreased wiring and control complexity, which lowers the computing latency and improves robustness and energy efficiency.

Devices, chips, and electronic equipment for sensing-memory-computing synergy

A computing-in-memory array, chip and electronic device includes a computing-in-memory array including at least one computing-in-memory cell having a first switch, a second switch, a third switch, a fourth switch, a coupling capacitor, a first bitline, a second bitline, a third bitline, a first wordline, a second wordline and a third wordline; a control module connected to the computing-in-memory array, which controls the voltages of each wordline and bitline to read and write data through the computing-in-memory array, or to perform computing-in-memory operations. By arranging the first switch, the second switch, the third switch, and the fourth switch in a differential form, and determining the stored value by the difference of the voltage between the two ports of the second switch and the third switch, the present embodiment of the disclosure can implement computing-in-memory operations with high accuracy, low circuit complexity, high reliability, and high energy efficiency. For memory function, the computing-in-memory device has a long data retention time and low data refresh overhead.

Devices, chips, and electronic equipment for computing-in-memory

The present disclosure relates to a memory device based on a ferroelectric capacitor, which includes a control unit for writing data into a memory cell or reading data from the memory cell and a plurality of memory cells arranged in an array; each memory cell includes an external interface, a first switch, a transistor, a first capacitor and a second capacitor, wherein at least one of the first capacitor and the second capacitor is a ferroelectric capacitor; the first switch has a first port connected with a first word line, a second port connected with a bit line, and a third port connected with one end of the first capacitor; and the transistor has a gate electrode connected with another end of the first capacitor and one end of the second capacitor, a source electrode connected with a first read terminal, and a drain electrode connected with a second read terminal, wherein another end of the second capacitor is connected with a second word line. According to the present disclosure, a polarized state of the ferroelectric capacitor in the memory cell is held or changed based on hysteresis characteristics of the ferroelectric capacitor, and the control unit is used to write data into or read data from the memory cell, which can implement non-destructive reading of data and longer endurance of a write operation.

Memory device based on ferroelectric capacitor

The present disclosure relates to a static random-access memory and an electronic device. The memory includes at least one storage circuit, wherein the storage circuit includes a first inverter, a second inverter, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a word-line, a first bit-line, a second bit-line, a shift-input line, and a shift-output line. The circuit is used to access data by using the first bit-line and/or the second bit-line when it works in a first mode, and the circuit is used to shift the input data to the shift-input line and output the shifted data through the shift-output line when it works in a second mode. By implementing shift-input and shift-output within the memory, the disclosed embodiment can achieve high-concurrency data access and data update, and it also enables high integration and low power consumption.

Static random-access memory and electronic device

The present disclosure discloses an SRAM cell circuit and an SRAM array circuit. The cell circuit includes a data storage module, a write operation module, and a read operation module. The data storage module consists of the component with the current-voltage hysteresis characteristic and is configured to store data with the current-voltage hysteresis characteristic. The data storage module includes a write operation port and a read operation port, and the data information stored in the data storage module may change without external energy input. The write operation module is coupled to the write operation port and is configured to perform write operation on the stored information. The write operation module ensures the stored information unchanged by continuously controlling the write operation port while not changing the stored information. The read operation module is coupled to the read operation port and configured to perform read operation on the stored information.

Static memory based on components with current-voltage hysteresis characteristics

In a data write control method, a write control apparatus currently runs a program in a write-back mode in which data are written to a volatile memory. When the apparatus detects that a quantity of dirty blocks in the volatile memory has reached a threshold, it predicts a first amount of execution progress of the program within a prediction time period under an assumption of the apparatus being in a write-through mode in which data are written to the volatile memory and a non-volatile memory. The apparatus also predicts a second amount of execution progress of the program within the prediction time period under an assumption of the apparatus being in the write-back mode. When the predicted first amount of execution progress exceeds the predicted second amount of execution progress, the apparatus switches from the write-back mode to the write-through mode.

Data write control apparatus and method

A data write control method includes detecting a quantity of dirty blocks in a first memory when a write control apparatus is in write-back mode; separately predicting execution progress of a program run by a processor within a danger time period in the two write modes when the quantity of dirty blocks reaches a first preset threshold; when it is predicted that the execution progress of the program run by the processor within the danger time period in write-through mode is faster than the execution progress of the program run by the processor within the danger time period in write-back mode, switching a current data write mode to the write-through mode; and detecting the quantity of dirty blocks when the write control apparatus is in write-through mode and switching the current data write mode to the write-back mode when the quantity of dirty blocks decreases to a second preset threshold.

When a data backup apparatus is powered on, a quantity of dead blocks and a quantity of live blocks are counted. After the data backup apparatus is powered off, a proportion occupied by dead blocks corresponding to each sequence access identifier at the power-on time point in a total quantity of sampled cache blocks corresponding to the sequence access identifier, is calculated according to the counted quantities of dead blocks and live blocks that correspond to the sequence access identifier at the time point when the data backup apparatus is powered on. The calculated proportion is compared with a preset threshold, and a dead block in a volatile memory unit is predicted according to a comparison result. During backup, a cache block that is predicted to be a dead block is not backed up.

Data backup apparatus and method

Provided are a method and a system for initializing an RF module through non-volatile control, including: storing, by a non-volatile storage array, configuration information for initializing the RF module, and backing up the configuration information when receiving a power-down instruction (S); and reading, by an RF module initialization accelerator, the configuration information from the non-volatile storage array when receiving a power-up instruction, and transmitting the read configuration information to the RF module, thereby initializing the RF module (S). With the technical solution given in the present invention, the initialization of an RF module becomes much faster, and the power consumption of a wireless communication terminal can be reduced. In addition, the initialization of various RF modules can be supported, and meanwhile the hardware resources can be saved, thereby enhancing the extensibility of the system.

Method and system for initializing RF module through non-volatile control

The present invention is a system and method for digital watermarking, which discloses a system for digital watermarking, to add a watermark to an audio signal generated by a signal source. The system comprises: a spectrum modulator configured to perform spectrum modulation to a watermark bit and a pseudo noise signal to be embedded into the audio signal to generate a modulated signal; a distortion controller coupled to the signal source and the spectrum modulator and configured to shape the modulated signal based on the audio signal, so as to generate a shaped signal satisfying a predetermined distortion constraint; and an interference compensator coupled to the signal source and the distortion controller and configured to generate a compensation signal based on the audio signal, the pseudo noise signal, and the shaped signal, wherein the compensation signal is for compensating for interference to watermark decoding caused by the audio signal.

Method and system for digital watermarking

Growing community of inventors

Beijing, China

Huazhong Yang