Mentor Graphics Corporation

Siemens Industry Software Gmbh

Other

Huaxing Tang

Wu-Tung Cheng

Manish Sharma

Robert Brady Benware

Janusz Rajski

Xiaoxin Fan

Yu Jane Huang

Gang Paul Chen

Chen Wang

Nagesh Tamarapalli

Jakub Janicki

Martin Keim

Gaurav Veda

Szczepan Urban

Wei Zou

Yue Tian

A computing system may include a model training engine configured to train a supervised learning model with a training set comprising training probability distributions computed for training dies through a local phase of a volume diagnosis procedure. The computing system may also include a volume diagnosis adjustment engine configured to access a diagnosis report for a given circuit die that has failed scan testing and compute, through the local phase of the volume diagnosis procedure, a probability distribution for the given circuit die from the diagnosis report. The volume diagnosis adjustment engine may also adjust the probability distribution into an adjusted probability distribution using the supervised learning model and provide the adjusted probability distribution for the given circuit die as an input to a global phase of the volume diagnosis procedure to determine a global root cause distribution for multiple circuit dies that have failed the scan testing.

Machine learning-based adjustments in volume diagnosis procedures for determination of root cause distributions

Various aspects of the disclosed technology relate to predicting physical failure analysis-oriented diagnosis resolution. Fault simulation is performed on a circuit design to derive test responses for a set of faults and test patterns for testing circuits fabricated according to the circuit design. The set of faults is grouped into groups of equivalent faults based on the test responses. A group of equivalent faults consists of faults having the same test responses for all test patterns in the test patterns that can activate the faults. A PFA (physical failure analysis)-oriented diagnosis resolution evaluation value is computed by averaging weighted sizes of the groups of equivalent faults. The weight factors for the groups of equivalent faults with sizes greater than a certain number being smaller than the weight factors for rest of the groups of equivalent faults.

Physical failure analysis-oriented diagnosis resolution prediction

This application discloses a computing system implementing an automatic test pattern generation tool to generate test patterns to apply to scan chains in an integrated circuit. The computing system can implement a defect diagnosis tool to simulate a circuit design describing an integrated circuit, inject faults from a fault list into the simulated circuit design, and apply the test patterns to the simulated circuit design. The computing system implementing the defect diagnosis tool can determine fault responses to the test patterns read from the simulated circuit design, which indicate a detection of the faults injected in the simulated circuit design, compress, for each of the faults in the fault list, the fault responses into fault signatures, consolidate the faults from the fault list into fault groups based on the fault signatures, and estimate a diagnosis resolution for the integrated circuit based, at least in part, on the fault groups.

Diagnosis resolution prediction

Various aspects of the disclosed technology relate to techniques of logic diagnosis based on cell-aware diagnostic pattern generation. A first diagnosis process is performed on a failed integrated circuit based on a first fail log to generate a first set of defect suspects. The first fail log is generated by applying the first set of test patterns to the failed integrated circuit in a first scan-based test. A second set of test patterns are generated using fault models for internal defects in one or more cells included in the first set of defect suspects. The second set of test patterns are applied to the failure integrated circuit to generate a second fail log. A second diagnosis process is performed on the failure integrated circuit based on the second fail log.

Cell-aware diagnostic pattern generation for logic diagnosis

Failing test pattern simulations are performed to determine initial defect suspects based on injecting faults to defect candidate sites which are derived based on test responses. Initial inter-cell bridge suspects are then determined from cells in the initial defect suspects based on layout information and electrical information of the circuit. Passing test pattern simulations are performed to determine inter-cell bridge suspects from the initial inter-cell bridge suspects.

Inter-cell bridge defect diagnosis

Logic diagnosis is performed on failing reports of defective integrated circuits to derive a diagnosis report for each of the failing reports which comprise information of suspects. The suspects comprise cell internal suspects and interconnect suspects. A probability distribution of root causes for causing the defective integrated circuits is determined to maximize a likelihood of observing the diagnosis reports based on a probability for each of the suspects given each of the root causes and a probability for each of the diagnosis reports given each of the suspects. The probability for each of the diagnosis reports given each of the cell internal suspects is weighted higher than the probability for each of the diagnosis reports given each of the interconnect suspects.

Cell-aware root cause deconvolution for defect diagnosis and yield analysis

Various aspects of the disclosed technology relate to circuit defect diagnosis based on sink cell fault models. Defect candidates are determined based on path-tracing from failing bits into the circuit design. Based on the defect candidates and one or more conventional fault models, failing test pattern simulations are performed to determine initial defect suspects. Initial defective sink cell suspects are then determined by comparing driving strengths for fan-out cells of the initial defect suspects with driving strengths for corresponding driver cells. Defective sink cell suspects may be identified in the initial defective sink cell suspects based on fault effect propagations and passing test pattern simulations.

Circuit defect diagnosis based on sink cell fault models

Aspects of the invention relate to techniques for fault diagnosis based on dynamic circuit design partitioning. According to various implementations of the invention, a sub-circuit is extracted from a circuit design based on failure information of one or more integrated circuit devices. The extraction process may comprise combining fan-in cones of failing observation points included in the failure information. The extraction process may further comprise adding fan-in cones of one or more passing observation points to the combined fan-in cones of the failing observation points. Clock information of test patterns and/or layout information of the circuit design may be extracted and used in the sub-circuit extraction process. The extracted sub-circuit may then be used for diagnosing the one or more integrated circuit devices.

Dynamic design partitioning for diagnosis

Aspects of the invention relate to techniques for chain fault diagnosis based on dynamic circuit design partitioning. Fan-out cones for scan cells of one or more faulty scan chains of a circuit design are determined and combined to derive a forward-tracing cone. Fan-in cones for scan cells of the one or more faulty scan chains and for failing observation points of the circuit design are determined and combined to derive a backward-tracing cone. By determining intersection of the forward-tracing cone and the backward-tracing cone, a chain diagnosis sub-circuit for the test failure file is generated. Using the process, a plurality of chain diagnosis sub-circuits may be generated for a plurality of test failure files. Scan chain fault diagnosis may then be performed on the plurality of chain diagnosis sub-circuits with a plurality of computers.

Dynamic design partitioning for scan chain diagnosis

Fault diagnosis techniques (e.g., effect-cause diagnosis techniques) can be speeded up by, for example, using a relatively small dictionary. Examples described herein exhibit a speed up of effect-cause diagnosis by up to about 160 times. The technologies can be used to diagnose defects using compacted fail data produced by test response compactors. A dictionary of small size can be used to reduce the size of a fault candidate list and also to facilitate procedures to select a subset of passing patterns for simulation. Critical path tracing can be used to handle failing patterns with a larger number of failing bits, and a pre-computed small dictionary can be used to quickly find the initial candidates for failing patterns with a smaller number of failing bits. Also described herein are exemplary techniques for selecting passing patterns for fault simulation to identify faults in an electronic circuit.

Speeding up defect diagnosis techniques

Aspects of the invention relate to techniques for fault diagnosis based on circuit design partitioning. According to various implementations of the invention, a circuit design of a failing die is first partitioned into a plurality of sub-circuits. The sub-circuits may be formed based on fan-in cones of observation points. Shared gate ratios may be used as a metric for adding fan-in cones of observation points into a sub-circuit. Based on test patterns and the sub-circuits, sub-circuit test patterns are determined. Fault diagnosis is then performed on the sub-circuits. The sub-circuit fault diagnosis comprises extracting sub-circuit failure information from the failure information for the failing die. The sub-circuit fault diagnosis may employ fault-free values for boundary gates in the sub-circuits.

Fault diagnosis based on design partitioning

Disclosed below are representative embodiments of methods, apparatus, and systems for generating test patterns having an increased ability to detect untargeted defects. In one exemplary embodiment, for instance, one or more deterministic test values for testing targeted faults (e.g., stuck-at faults or bridging faults) in an integrated circuit design are determined. Additional test values that increase detectability of one or more untargeted defects during testing are determined. One or more test patterns are created that include at least a portion of the deterministic test values and at least a portion of the additional test values. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods or comprising test patterns generated by any of the disclosed embodiments are also disclosed.

Generating test patterns having enhanced coverage of untargeted defects

Methods, apparatus, and systems for testing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, one or more fault dictionaries are generated for identifying one or more defect candidates from corresponding observation point combinations. In this exemplary method, the observation point combinations indicate the observation points of a circuit-under-test that captured faulty test values upon application of a respective test pattern. Further, the one or more fault dictionaries in one embodiment are generated by: (a) for a first defect candidate, storing one or more first indicators indicative of test patterns detecting the first defect candidate, and (b) for a second defect candidate, storing at least a second indicator indicative of the test patterns that detect the second defect candidate, the second indicator comprising a bit mask that indicates which of the test patterns detecting the first defect candidate also detect the second defect candidate.

Fault dictionaries for integrated circuit yield and quality analysis methods and systems

Methods, apparatus, and systems for computing and analyzing integrated circuit yield and quality are disclosed herein. For example, in one exemplary method disclosed herein information is received from processing test responses of integrated circuits designed for functional use in electronic devices. In this embodiment, the information is indicative of integrated circuit failures observed during testing of the integrated circuits and of possible yield limiting factors causing the integrated circuit failures. Probabilities that one or more of the possible yield limiting factors in the integrated circuits actually caused the integrated circuit failures are determined by statistically analyzing the received information. The probabilities that one or more possible yield limiting factors actually caused the integrated circuit failures are reported. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the described methods are also disclosed.

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Wilsonville, OR, United States of America

Huaxing Tang