Chinese Academy of Sciences

Juniper Networks, Inc.

Huaxiang Yin

Qiuxia Xu

Dapeng Chen

Xiaolong Ma

Changliang Qin

Huilong Zhu

Qingzhu Zhang

Zuozhen Fu

Chao Xi Chen

Xiao Ping Zhu

Zheling Yang

Jiang Yan

Tianchun Ye

Tao Yang

Wenwu Wang

Guilei Wang

Lingkuan Meng

Qingqing Liang

Chao Zhao

Junfeng Li

Hong Yang

Yongliang Li

Jinbiao Liu

Sen Xu

Xiaohong Cheng

Zhaohao Zhang

Weijia Xu

Jiaxin Yao

Haizhou Yin

Huicai Zhong

Jun Luo

Jing Zhang

Gaobo Xu

Junjie Li

Kai Han

Xiaolei Wang

Lei Liang

Honggang Liu

Zengqiang Yuan

Yongkui Zhang

Lichuan Zhao

Zhiguo Zhao

Xueli Ma

Mingming Quan

Henry H Radamson

Zhiyong Lu

Xiongkun Yang

Changliang Qi

Peizhen Hong

Lingkkuan Meng

Dapeng Cheng

BinFang Sun

Zhenzhen Kong

Gaofeng Tian

Renren Xu

Zhaozhao Hou

Chaolei Li

Provided are a three-dimensional vertical single transistor ferroelectric memory and a manufacturing method thereof. The ferroelectric memory comprises: a substrate; an insulating dielectric layer provided at the substrate; a channel structure extending through the insulating dielectric layer and connected to the substrate, the channel structure having a source/drain region and a channel region connected to the source/drain region; and a gate stack structure arranged around the channel structure and provided in the insulating dielectric layer opposite to the channel region, the gate stack structure comprising a ferroelectric insulation layer and a gate sequentially stacked in a direction away from the channel structure. The ferroelectric memory having the above structure can replace conventional DRAMs. Therefore, the invention realizes a high intensity high speed memory.

Three-dimensional vertical single transistor ferroelectric memory and manufacturing method thereof

A gate-all-around nanowire device and a method for forming the gate-all-around nanowire device. A first fin and a dielectric layer on the first fin are formed on a substrate. The first fin includes the at least one first epitaxial layer and the at least one second epitaxial layer that are alternately stacked. The dielectric layer exposes a channel region of the first fin. A doping concentration at a lateral surface of the channel region and a doping concentration at a central region of the channel region are different from each other in the at least one second epitaxial layer. After the at least one first epitaxial layer is removed from the channel region, the at least one second epitaxial layer in the channel region serves as at least one nanowire. A gate surrounding the at least one nanowire is formed.

Method for forming gate-all-around nanowire device

A stacked nanowire or nanosheet gate-all-around device, including: a silicon substrate; stacked nanowires or nanosheets located on the silicon substrate, extending along a first direction gate stacks and including multiple nanowires or nanosheets that are stacked; a gate stack, surrounding each of the stacked nanowires or nanosheets, and extending along a second direction, where first spacers are located on two sidewalls of the gate stack in the first direction; source-or-drain regions, located at two sides of the gate stack along the first direction; a channel region, including a portion of the stacked nanowires or nanosheets that is located between the first spacers. A notch structure recessed inward is located between the stacked nanowires or nanosheets and the silicon substrate, and includes an isolator that isolates the stacked nanowires or nanosheets from the silicon substrate. A method for manufacturing the stacked nanowire or nanosheet gate-all-around device is further provided.

Stacked nanowire or nanosheet gate-all-around device and method for manufacturing the same

A semiconductor device and a method for manufacturing the semiconductor device. Multiple stacks and an isolation structure among the multiple stacks are formed on a substrate. Each stack includes a first doping layer, a channel layer and a second doping layer. For each stack, the channel layer is laterally etched from at least one sidewall of said stack to form a cavity located between the first doping layer and the second doping layer, and a gate dielectric layer and a gate layer are formed in the cavity. A first sidewall of each stack is contact with the isolation structure, and the at least one sidewall does not include the first side wall. Costly high-precision etching is not necessary, and therefore a device with a small size and a high performance can be achieved with a simple process and a low cost. Diversified device structures can be provided on requirement.

Semiconductor device and method for manufacturing the same

A method for manufacturing a stacked gate-all-around nano-sheet CMOS device, including: providing a substrate with a fin structure, where a channel layer for an NMOS is a sacrificial layer for a PMOS, a channel layer for the PMOS is a sacrificial layer for the NMOS; and mobility of holes in the second material is greater than mobility of holes in the first material; forming a dummy gate stack extending across the fin structure; forming source-or-drain regions in the fin structure at two sides of the dummy gate stack; removing the dummy gate stack and the sacrificial layers covered by the dummy gate stack, to expose a surface of a part of the channel layer that is located between the source-or-drain regions, where a nano-sheet array is formed by the channel layer with the exposed surface; and forming a gate stack structure surrounding each nano sheet in the nano-sheet array.

Structure of stacked gate-all-around nano-sheet CMOS device and method for manufacturing the same

A method for manufacturing a semiconductor device is provided. A first substrate and at least one second substrate are provided. A single crystal lamination structure is formed on the first substrate. The single crystal lamination structure includes at least one hetero-material layer and at least one channel material layer that are alternately laminated, each of the at least one hetero-material layer is bonded to an adjacent one of the at least one channel material layer at a side away from the first substrate, and each of the at least one channel material layer is formed from one of the at least one second substrate. At least one layer of nanowire or nanosheet is formed from the single crystal lamination structure. A gate dielectric layer and a gate which surround each of the at least one layer of nanowire or nanosheet is formed. A semiconductor device is also provided.

A negative capacitance field effect transistor (NCFET) and a manufacturing method thereof. The NCFET includes: a substrate structure, including a MOS region; a gate insulating dielectric structure, covering the MOS region; and a metal gate stack layer, covering the gate insulating dielectric structure. The gate insulating dielectric structure includes an interface oxide layer, a HfOlayer, a doping material layer, and a ferroelectric material layer, which are sequentially stacked along a direction away from the substrate structure. A ferroelectric material in the ferroelectric material layer is HfAO, A represents a doping element, and 0.1&#x2264;x&#x2264;0.9. A material forming the doping material layer is AOor A, and a ratio of y/z is equal to 1/2, 2/3, 2/5 or 1/1. Ferroelectric characteristics, material stability, and material reliability of the NCFET are improved by increasing domain polarity of the ferroelectric material.

Negative capacitance field effect transistor and method for manufacturing the same

A semiconductor device, including: a silicon substrate; multiple fin structures, formed on the silicon substrate, where each extends along a first direction; a shallow trench insulator, located among the multiple fin structures; a gate stack, intersecting with the multiple fin structures and extending along a second direction, where first spacers are formed on two sidewalls in the first direction of the gate stack; source-or-drain regions, formed on the multiple fin structures, and located at two sides of the gate stack along the first direction; and a channel region, including a portion of the multiple fin structures located between the first spacers. and notch structures. A notch structure recessed inward is located between each of the multiple fin structures and the silicon substrate. The notch structure includes an isolator that isolates each of the multiple fin structures from the silicon substrate.

A device may comprise security processing units (SPUs) including a SPU to receive a session request. The SPU may identify global counter information and update counter information. The global counter information may include a global counter identifier and a global counter value. The update counter information may include an update counter identifier and an update counter value. The SPU may identify a global limit associated with the global counter, may determine that the global limit has not been met, and may cause the session to be created. The SPU may create a modified global counter value. The SPU may create a modified update counter value. The SPU may determine that a local update message is required based on the modified update counter value, and may provide the local update message to another SPU. The local update message may include the global counter identifier and the modified global counter value.

State synchronization for global control in a distributed security system

A first processing device may receive, from a first network device, a tunneling protocol message associated with a tunnel to be established between the first network device and a second network device. The first processing device may determine, based on the tunneling protocol message, a device identifier of the second network device. The first processing device may determine that a second processing device is to process a flow associated with the first network device and the second network device based on the device identifier of the second network device. The first processing device may provide information that identifies that the second processing device is to process the flow to permit the second processing device to process the flow associated with the first network device and the second network device.

Flow processing migration

A device includes a security process unit (SPU) associated with a logical ring of SPUs. The SPU receives a packet with an address associated with a malicious source, and creates, based on the packet, an entry in a data structure associated with the SPU. The entry includes information associated with the packet. The SPU provides an install message to a next SPU in the logical ring. The install message instructs the next SPU to create the entry in another data structure, and forward the install message to another SPU. The SPU receives the install message from a last SPU, and sets a state of the entry to active in the data structure based on receiving the install message from the last SPU. The SPU performs a particular action on another packet, associated with the malicious source, based on the setting the state of the entry to active.

Distributed learning and aging for management of Internet protocol (IP) addresses

A method for forming a metal silicide. The method comprises: providing a substrate having a fin, a gate formed on the fin, and spacers formed on opposite sides of the gate; depositing a Ti metal layer; siliconizing the Ti metal layer; and removing unreacted Ti metal layer. As the Ti atoms have relatively stable characteristics, diffusion happens mostly to Si atoms while the Ti atoms rarely diffuse during the thermal annealing. As a result, current leakage can be prevented in a depletion region and thus leakage current of the substrate can be reduced.

Methods for forming metal silicide

A MOS transistor with stacked nanowires and a method of manufacturing the same. The transistor may include a stack of cascaded nanowires extending in a first direction on a substrate; a gate stack extending in a second direction across the nanowire stack; source and drain regions disposed on opposite sides of the gate stack in the second direction; and a channel region constituted of the nanowire stack between the source and drain regions. The cascaded nanowires can be formed by repeated operations of etching back, and lateral etching and then filling of grooves, thereby increasing an effective width of the channel, increasing a total area of an effective conductive section, and thus improving a drive current.

Method of manufacturing MOS transistor with stack of cascaded nanowires

Methods of manufacturing stacked nanowires MOS transistors are disclosed. In one aspect, the method includes forming a plurality of fins along a first direction on a substrate. The method also includes forming stack of nanowires constituted of a plurality of nanowires in each of the fins. The method also includes forming a gate stack along a second direction in the stack of nanowires, the gate stack surrounding the stack of nanowires. The method also includes forming source/drain regions at both sides of the gate stack, the nanowires between the respective source/drain regions constituting a channel region. A stack of nanowires may be formed by a plurality of etching back, laterally etching a trench and filling the trench. The laterally etching process includes isotropic dry etching having an internally tangent and lateral etching, and a wet etching which selectively etches along respective crystallographic directions.

Method of manufacturing stacked nanowire MOS transistor

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Beijing, China

Huaxiang Yin