Spansion Llc.

Cornell University

Cypress Semiconductor Corporation

Huaqiang Wu

Ning Cheng

Chungho Lee

Hiro Kinoshita

Kuo-Tung Chang

Angela Tai Hui

Hiroyuki Kinoshita

Jihwan Choi

Minghao Shen

Lei Xue

Michael Spencer

Fred Cheung

Calvin T Gabriel

Chih-Yuh Yang

Harpreet Kaur Sachar

Francis J DiSalvo

Phillip Lawrence Jones

Wai Lo

Shenqing Fang

Chi K Chang

Emmanuel P Giannelis

Rinji Sugino

Yuri Makarov

Christie R K Marrian

Arturo Ruiz

Phani Konkapaka

Athanasios Bourlinos

Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.

HTO offset for long leffective, better device performance

Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.

Oro and orpro with bit line trench to suppress transport program disturb

HTO offset for long Leffective, better device performance

Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.

Gate replacement with top oxide regrowth for the top oxide improvement

Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.

HTO offset and BL trench process for memory device to improve device performance

Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved.

Sacrificial nitride and gate replacement

Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.

Split charge storage node outer spacer process

ORO and ORPRO with bit line trench to suppress transport program disturb

Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a pair of first bit lines and a pair of second bit lines. The first and second bit lines can be formed by an implant process using first and second spacers that have different lateral lengths from each other. The spacers can be used to offset the implants, thereby controlling the lateral lengths of the bit lines.

HTO offset spacers and dip off process to define junction

Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.

Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics

GaN is grown by creating a Ga vapor from a powder, and using an inert purge gas from a source to transport the vapor to a growth site where the GaN growth takes place. In one embodiment, the inert gas is N, and the powder source is GaN powder that is loaded into source chambers. The GaN powder is congruently evaporated into Ga and Nvapors at temperatures between approximately 1000 and 1200&#xb0; C. The formation of Ga liquid in the powder is suppressed by the purging of an inert gas through the powder. The poser may also be isolated from a nitride containing gas provided at the growth cite. In one embodiment, the inert gas is flowed through the powder.

GaN bulk growth by Ga vapor transport

Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing exposed portions of a first poly layer while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing exposed portions of a charge storage layer while leaving portions of the charge storage layer protected by the two split sub-lithographic first poly gates, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.

Split charge storage node inner spacer process

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Mountain View, CA, United States of America

Huaqiang Wu