Yangtze Memory Technologies Co., Ltd.

Huangpeng Zhang

Yu Wang

Qi Wang

Xiaodong Mei

Daesik Song

Ke Jiang

Xiang Fu

Zhichao Du

Shiyang Yang

Cong Luo

Debo Wei

Ting Li

Huamin Cao

Xu Hou

Jinze Song

Zhefan Li

According to one aspect of the present disclosure, a memory is provided. The memory may include a row hammer control circuit including a plurality of counters. Each of the plurality of counters may count a number of accesses of one memory row. Each of the plurality of counters may be configured to generate a first count value. The memory may include an adjustment circuit connected with the plurality of counters. The adjustment circuit may reset each of the plurality of counters when each of a plurality of first count values reaches a target threshold. The adjustment circuit may adjust each of the first count values by a same offset value to generate a plurality of second count values. The row hammer control circuit may determine a target memory row according to the plurality of second count values.

Memory and operation method thereof and memory system

Examples of the present application provide operation methods of memories, memory devices and systems. In an example, an operation method includes: in response to a first defective memory cell row of a plurality of memory cell rows in the memory being repaired before packaging, invalidating, in a post-package repair mode, a first repair strategy for repairing the first defective memory cell row before packaging, and configuring a second repair strategy for repairing the first defective memory cell row and storing the second repair strategy.

Operation method of memory, memory and memory system

A memory device includes a first logic unit (LUN) and a second LUN. The first LUN is coupled to the second LUN and configured to receive a first multi-plane operation command of a set of multi-plane operation commands corresponding to the first LUN, latch a first address of the first multi-plane operation command into a first address register of the first LUN, receive a single-plane operation command that includes a second address and corresponds to the second LUN, and keep latching the first address into the first address register.

Bus-interleave protocol to improve multiple logic unit (LUN) operation efficiency

In certain aspects, a memory device includes memory cells, word lines coupled to the memory cells, and a peripheral circuit coupled to the memory cells. The peripheral circuit is coupled to the word lines and configured to apply program pulses to a selected word line of the word lines in a program operation, obtain a number of occurrences of suspensions during the program operation, and determine a limit on a number of program pulses for the program operation based on the number of occurrences of the suspensions during the program operation.

Memory device and program operation thereof

A method of configuring an on-die termination circuit in each non-volatile memory die of a plurality of non-volatile memory dice that have one or more pads coupled in common, includes determining, by each of the non-volatile memory dice whether that non-volatile memory die is a target or a non-target for a memory operation; setting, by each of the non-volatile memory die that determines it is a target, a first on-die termination configuration value; setting, by each of the non-volatile memory die that determines it is a non-target, a second on-die termination configuration value; configuring, by each of the target non-volatile memory die, its corresponding on-die termination circuit to provide a first impedance based, at least in part, on the first on-die termination configuration value; and concurrently with the configuring by each target non-volatile memory die, configuring, by each non-target non-volatile memory die, its corresponding on-die termination circuit to provide a second impedance based, at least in part, on the second on-die termination configuration value.

On-die termination configuration for integrated circuit

Disclosed herein are memory device, method for managing a storage system. In an aspect, a memory device comprises an address register to store addresses and a processor coupled to the address register. The processor is configured to receive a first multi-plane program operation command of a set of multi-plane program operation commands. The processor is further configured to latch a first address of the first multi-plane program operation command into the address register. In addition, the processor is further configured to receive a read operation command that includes a second address and refrain from latching the second address into the address register.

In certain aspects, a circuit for ZQ resistor calibration can include a first input configured to receive a first default configuration. The circuit can also include a second input configured to receive a first calibration value based on a first comparison. The circuit can further include a first output configured to provide a first resistor code for a first resistor category. The circuit can additionally include a second output configured to provide a second resistor code for a second resistor category different from the first resistor category. The circuit can also include a first logic circuit configured to receive a signal from the first input and a signal from the second input, and provide a signal to the first output. The signal to the first output can include the first resistor code. The first resistor code can be different from the second resistor code.

ZQ resistor calibration circuit in memory device and calibration method thereof

In certain aspects, a memory device includes memory cells, and a peripheral circuit coupled to the memory cells. The peripheral circuit is configured to initiate a program operation on a selected memory cell of the memory cells, obtain a number of occurrences of one or more suspensions during the program operation, and determine a program pulse limit for the program operation based on the number of occurrences of the suspensions.

Aspects of the disclosure provide a semiconductor memory device. The semiconductor memory device includes a memory cell array and peripheral circuitry coupled with the memory cell array. The memory cell array includes a plurality of memory cells. The peripheral circuitry includes programmable logic circuit that is configured, after the semiconductor memory device is powered on, to perform logic functions.

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Wuhan, China

Huangpeng Zhang