Taiwan Semiconductor Manufacturing Comp. Ltd.

Huang-Yu Chen

Chung-Hsing Wang

Yuan-Te Hou

Lee-Chung Lu

Chin-Hsiung Hsu

Ken-Hsien Hsieh

Yi-Kan Cheng

Wen-Hao Chen

Ru-Gun Liu

Li-Chun Tien

Tsong-Hua Ou

Jerry Chang Jui Kao

Yi-Lin Chuang

Yun-Han Lee

Hui-Zhong Zhuang

Sheng-Hsiung Chen

Wen-Ju Preet Yang

Yung-Chen Chien

King-Ho Tam

Fang-Yu Fan

Yu-Hsiang Kao

Gwan Sin Chang

Hsiao-Shu Chao

Yu-Ze Lin

Shin-Chi Chen

Wen-Chun Huang

Chin-Chang Hsu

Cheng-I Huang

Chung-Min Fu

Wei-Hsiang Ma

Cheng-Yu Lin

Wei-Ren Chen

Fung Song Lee

Dio Wang

Jhih-Jian Wang

Ming-Feng Shieh

Kuo-Nan Yang

Jack Liu

Jui-Feng Kuan

Pin-Dai Sue

Chin-Shen Lin

Ke-Ying Su

Ching-Fang Chen

Chi-Yeh Yu

Wan-Yu Lo

Shao-Huan Wang

Tzu-Ying Lin

Zhe-Wei Jiang

Yen-Pin Chen

Ho Che Yu

Ching-Shun Yang

Yi-Chuin Tsai

Cheng Kun Tsai

Hung Lung Lin

Ying-Yu Shen

Tan-Li Chou

Ya Chen Wang

Chia Cheng Chen

Lee Fung Song

Jen Ping Hsu

A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device, subject to a limiting condition, such as one determined using a cost function. A computer system including one or more EDAs configured to perform the method is also disclosed.

Automated system and method for circuit design

A device is disclosed that includes multiple channels and multiple processing nodes. Each processing node includes input/output (I/O) ports coupled to the channels and channel control modules coupled to the I/O ports. Each processing node is configured to select, by the channel control module in a first operation, a first I/O port of the I/O ports; communicate a first message, via the first I/O port, to a first processing node over a first channel or a second processing node over a second channel orthogonal to the first channel in a logic representation; select, by the channel control module in a second operation, a second I/O port of the I/O ports; and communicate a second message, via the second I/O port, to a third processing node over a third channel extending in a diagonal direction and non-orthogonal to the first and second channels in the logic representation.

Diagonal torus network

An integrated circuit (IC) device includes a substrate, at least one active region over the substrate and elongated along a first axis, at least one gate region extending across the at least one active region, and at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to other circuitry. The at least one IO pattern extends obliquely to the at least one active region or the at least one gate region.

Integrated circuit device and method

A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first width of at least one first metal interconnect is different from a second width of one of the plurality of second metal interconnects.

Cell layout of semiconductor device

A method includes: providing a first layout of a first layer over a substrate, the first layer having at least one metal pattern, and generating a second layout by placing a cut mask at a first position relative to the substrate to remove material from a first region of the at least one metal pattern to provide a first metal pattern and placing the cut mask at a second position relative to the first layer over the substrate to remove material from a second region of the at least one metal pattern to provide a second metal pattern.

Method of cutting conductive patterns

A clock distribution system includes a clock mesh structure which has a plurality of first metal patterns extending along a first axis, a plurality of second metal patterns extending along a second axis, a plurality of third metal patterns extending along a third axis. The plurality of first metal patterns, the plurality of second metal patterns, and the plurality of third metal patterns are electrically coupled with each other. The second axis is transverse to the first axis. The third axis is oblique to both the first axis and the second axis.

Clock signal distribution system, integrated circuit device and method

The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.

Conductor scheme selection and track planning for mixed-diagonal-manhattan routing

An integrated circuit (IC) device includes a substrate, and a cell over the substrate. The cell includes at least one active region and at least one gate region extending across the at least one active region. The cell further includes at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to external circuitry outside the cell. The at least one IO pattern extends obliquely to both the at least one active region and the at least one gate region.

A method for manufacturing a semiconductor device is provided. The method comprises determining a dimensional quantity of a layout pattern having an angle relative to grid lines of a minimum grid. The minimum grid may be defined by a first quantity associated with a first direction and a second quantity associated with a second direction perpendicular to the first direction. The determination of the dimensional quantity of the layout pattern is based on the first quantity, the second quantity and the angle of the layout pattern relative to the grid lines of the minimum grid.

Circuit layouts and related methods

A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device. A computer system including one or more EDAs configured to perform the method is also disclosed.

A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first via connects the first metal interconnect to the pin, and the at least one first metal interconnect is perpendicular to the pin.

Conductor scheme selection and track planning for mixed-diagonal-Manhattan routing

A method, includes: extracting a design data using a computer, wherein the design data includes a net name and a connective layer name of each layout design in each cell; generating a layout pattern corresponding to the design data by assigning an ID to said each layout design, wherein the ID includes a first indicator indicative of the net name and a second indicator indicative of the connective layer name; and checking the layout pattern to locate an error of the layout pattern.

Method and associated system for circuit design

Growing community of inventors

Zhudong, Taiwan

Huang-Yu Chen