Taiwan Semiconductor Manufacturing Comp. Ltd.

Huang-Sheng Lin

Shan-Yu Huang

Hsiao-Wen Chung

Hsien-Wei Chen

Chung-Min Fu

Yi-Lun Chen

Yu-Chyi Harn

Yilun Chen

Shih-Chang Chen

Fu-Jier Fan

Sheng-Chi Chin

Ho-Yin Yiu

Ruey-Yun Shiue

Yu-Jui Wu

Ming-Hsien Chen

Aaron Wang

Hsiang-Wei Wang

Shouh-Dauh Fred Lin

Lawrence Chen

Chun-Mai Liu

A semiconductor structure includes first and second inner seal rings each having a first section and a second section substantially perpendicular to the first section. The semiconductor structure further includes an outer seal ring. The outer seal ring has a third section, and a fourth section, and a fifth section. The semiconductor structure further includes dummy patterns substantially uniformly distributed in each of regions between the first inner seal ring and the outer seal ring and between the second inner seal ring and the outer seal ring.

Dummy patterns in redundant region of double seal ring

A semiconductor structure includes a first circuit region; a first inner seal ring at least partially surrounding the first circuit region; and an outer seal ring at least partially surrounding the first inner seal ring. The outer seal ring includes a first corner and a substantially triangular corner seal ring (CSR) structure at the first corner. The first inner seal ring includes a second corner adjacent to and spaced away from the CSR structure. The semiconductor structure further includes a first region between a first side of the first corner and a first side of the second corner that is parallel to the first side of the first corner, and multiple functional patterns in the first region.

Semiconductor device having functional patterns in redundant regions of double seal ring

A semiconductor structure is provided. The semiconductor structure includes two circuit regions, two inner seal rings, an outer seal ring, a first redundant region, and an electrical circuit. Each of the inner seal rings surrounding one of the circuit regions. The outer seal ring is disposed around the inner seal rings, and each of the inner seal rings contacts the outer seal ring at different interior corners of the outer seal ring. The first redundant region is located between at least one of the inner seal rings and the outer seal ring. The electrical circuit is formed in the first redundant region and electrically connected to at least one of the circuit regions.

Semiconductor structure and method for forming features in redundant region of double seal ring

A semiconductor structure that includes two circuit regions; two inner seal rings, each of the two inner seal rings surrounding one of the two circuit regions; an outer seal ring surrounding the two inner seal rings, wherein each of the inner seal rings and the outer seal ring has a substantially rectangular periphery with four interior corner seal ring structures; four first redundant regions between the two inner seal rings and the outer seal ring, each of the four first redundant regions being a substantially trapezoidal shape; and first dummy patterns substantially uniformly distributed in the four first redundant regions.

A semiconductor coupon-service system, includes a coupon-service module for managing a semiconductor service; a coupon generator, in connection with the semiconductor service, for generating a coupon associated with the semiconductor service; and a coupon maintainer, in connection with the semiconductor service, for processing coupon operations associated with the coupon.

Coupon-point system for managing supportive services to business in a semiconductor foundry environment

A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.

Integrated stress relief pattern and registration structure

Top via pattern for a bond pad structure has at least one first via group and at least one second via group adjacent to each other. The first via group has at least two line vias extending in a first direction. The second via group has at least two line vias extending in a second direction different from said first direction. The line via of the first via group does not cross the line via of the second via group.

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Hsin-Chu, Taiwan

Huang-Sheng Lin