Taiwan Semiconductor Manufacturing Comp. Ltd.

Young Optics Inc.

Huang-Ming Chen

Huan-Just Lin

Ching-Hua Hsieh

Hsueh Wen Tsau

Li-Lin Su

Yu-Lien Huang

Tsai-Chun Li

Yang-Cheng Wu

Cheng-Hua Yang

Mei-Yun Wang

Chao-Cheng Chen

Hun-Jan Tao

Chii-Ming M Wu

Chun-Feng Nieh

Ming-Ta Lei

Chien-An Chen

Chu-Ming Cheng

Guan-Ren Wang

Fang-Cheng Chen

Chia-Han Lai

Chun-Li Chou

Peng Wang

Yung-Chung Chen

Yun-Min Chang

Pei-Chao Su

Wen-Chi Tsai

Jiunn-Lih Lin

Yu-Chen Su

Jyu-Horng Shieh

Chih-Hsien Tsai

Chien-Chih Chiu

Chien-Han Chen

Pei-Ching Liu

Shih-Yu Chang

Po-Jen Chung

Tien-Pao Chen

Tzu-Kai Wang

A method includes forming a transistor comprising a source/drain region and a gate electrode, forming a source/drain contact plug over and electrically connecting to the source/drain region, forming a first inter-layer dielectric over the source/drain contact plug, forming an etch stop layer over the first inter-layer dielectric, etching the etch stop layer to form a first via opening, forming a second inter-layer dielectric over the first inter-layer dielectric, performing an etching process, so that the second inter-layer dielectric is etched to form a trench, and the first via opening in the etch stop layer is extended into the first inter-layer dielectric to reveal the source/drain contact plug, and filling the trench and the first via opening in common processes to form a metal line and a via, respectively.

Dual damascene structure in forming source/drain contacts

A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.

Copper contact plugs with barrier layers

A method includes forming an inter-layer dielectric over a first source/drain region and a second source/drain region. The first source/drain region and the second source/drain region are of n-type and p-type, respectively. The inter-layer dielectric is etched to form a first contact opening and a second contact opening, with the first source/drain region and the second source/drain region exposed to the first contact opening and the second contact opening, respectively. A process gas is used to etch back the first source/drain region and the second source/drain region simultaneously, and a first etching rate of the first source/drain region is higher than a second etching rate of the second source/drain region. A first silicide region and a second silicide region are formed on the first source/drain region and the second source/drain region, respectively.

Selective NFET/PFET recess of source/drain regions

Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.

Methods for controlling an end-to-end distance in semiconductor device

A system and method for forming and using a liner is provided. An embodiment comprises forming an opening in an inter-layer dielectric over a substrate and forming the liner along the sidewalls of the opening. A portion of the liner is removed from a bottom of the opening, and a cleaning process may be performed through the liner. By using the liner, damage to the sidewalls of the opening from the cleaning process may be reduced or eliminated. Additionally, the liner may be used to help implantation of ions within the substrate.

Semiconductor device and method for forming the same

An embodiment is a method comprising diffusing carbon through a surface of a substrate, implanting carbon through the surface of the substrate, and annealing the substrate after the diffusing the carbon and implanting the carbon through the surface of the substrate. The substrate comprises a first gate, a gate spacer, an etch stop layer, and an inter-layer dielectric. The first gate is over a semiconductor substrate. The gate spacer is along a sidewall of the first gate. The etch stop layer is on a surface of the gate spacer and over a surface of the semiconductor substrate. The inter-layer dielectric is over the etch stop layer. The surface of the substrate comprises a surface of the inter-layer dielectric.

Methods for introducing carbon to a semiconductor structure and structures formed thereby

Methods for introducing carbon to a semiconductor structure

A method for preventing the formation of contaminating polymeric films on the backsides of semiconductor substrates includes providing an oxygen-impregnated focus ring and/or an oxygen-impregnated chuck that releases oxygen during etching operations. The method further provides delivering oxygen gas to the substrate by mixing oxygen in the cooling gas mixture, maintaining the focus ring at a temperature no greater than the substrate temperature during etching and cleaning the substrate using a two step plasma cleaning sequence that includes suspending the substrate above the chuck.

Method for backside polymer reduction in dry-etch process

Growing community of inventors

Hsinchu, Taiwan

Huang-Ming Chen