Globalfoundries Inc.

Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Hefechip Corporation Limited

Other

Huang Liu

Hong Yu

Haigou Huang

Hai Cong

Jin Ping Liu

Wei Lu

Zhiguo Sun

Jinping Liu

Liang Choo Hsia

Huy Cao

Zheng Zou

Johnny Widodo

Alex See

Xintuo Dai

Zhao Lun

Alex K H See

Sandeep Gaan

Songkram Srivathanakul

John Leonard Sudijono

Sipeng Gu

Xiang Hu

Chung Woh Lai

Shailendra Mishra

Seung Yeon Kim

Hung-Wei Liu

John H Zhang

Juan Boon Tan

Mei Sheng Zhou

Guillaume Bouche

James Yong Meng Lee

Lup San Leong

Liang-Choo Hsia

Yun Ling Tan

Xuesong Rao

Liang Li

Meisheng Zhou

Hui Peng Koh

Alex Kai Hung See

Wen Zhi Gao

Yanzun Li

Garo Jacques Derderian

Jiehui Shu

Guoxiang Ning

Chim Seng Seet

Shiang Yang Ong

Richard J Carter

Hongliang Shen

Chun Yu Wong

Feng Chen

Tsung-Liang Chen

Changyong Xiao

Yuping Ren

Chin Teong Lim

Qiang Fang

Alan Cuthbertson

Fang Chen

Haifeng Sheng

Wen-Pin Peng

Sarasvathi Thangaraju

Hsin-Neng Tai

Peter Chew

Wei Hua Tong

Weihua Tong

Arthur Ang

James Yongmeng Lee

Wen Zhan Zhou

Jean-Baptiste Laloe

Sang Cheol Han

Devendra K Sadana

Hui Zang

Min-Hwa Chi

Haiting Wang

Andy C Wei

Jianwei Peng

Soh Yun Siah

Suraj Kumar Patil

Bei Chao Zhang

Bharat V Krishnan

Charles Lin

Jinsheng Gao

Matthew W Stoker

Wuping Liu

Chun Hui Low

Hoong Shing Wong

Hui Zhan

Chang Ho Maeng

Lun Zhao

Wonwoo Kim

Bangun Indajang

Wang Zheng

Luona Goh

Yiqun Liu

Hyucksoo Yang

Guoliang Zhu

Kenneth Andrew Bates

Shyam Pal

Wenzhi Gao

Zhehui Wang

Jiong Li

Danni Chen

A semiconductor structure and a method of forming it are disclosed by the present application. Deep trench capacitors are formed in a substrate, and fin contacts formed by upper portions of inner electrodes in the deep trench capacitors are connected to fins on a surface of the substrate. At least one of word lines formed on the substrate pass over and are separated by a word line isolation layer from the inner electrodes. The word line isolation layer covers portions of the inner electrodes between a buried oxide layer and the fin contacts, while the fins are exposed therefrom.

Semiconductor structure and forming method thereof

A method to form a fin structure on deep trenches (DTs) for a semiconductor device includes the following steps: A buried oxide layer (BOX) having the DTs, and silicon polies in the DTs is provided. A fin on the BOX and the silicon polies having poly fences is provided. A first mask is disposed on the fin. A liner is disposed on the BOX and the first mask, wherein the liner has a first part above the fin, a second part at lateral sides of the fin and a third part on the DTs and the BOX. A second mask is disposed on the first and the second parts of the liner. The second mask and the third parts of the liner are removed to reveal the first and the second parts of the liner. The poly fences are removed and spacers at the lateral sides are formed.

Method to form a fin structure on deep trenches for a semiconductor device

A semiconductor device for a volatile memory is disclosed. The semiconductor device includes a substrate, a side wall and an epitaxial liner. The substrate has a first height and is made of a first material having a first lattice parameter. The side wall defines a deep trench. The epitaxial liner is disposed around the side wall, is made of a second material having a second lattice parameter, and has a second height having a same level with the first height, wherein the epitaxial liner and the side wall cooperate for creating a desired aspect ratio for the deep trench.

Semiconductor device for a volatile memory and method of manufacturing semiconductor device

A semiconductor device including a silicon-on-insulator (SOI) wafer comprising a doped silicon substrate, a buried oxide layer on the doped silicon substrate, and a silicon device layer on the buried oxide layer. An inner electrode and a node dielectric layer of a capacitor are disposed in a trench of the SOI wafer. The inner electrode and the node dielectric layer penetrate through the buried oxide layer and extend into the doped silicon substrate. At least a select transistor is disposed on the buried oxide layer. The select transistor includes a source doping region and a drain doping region, a channel region between the source doping region and the drain doping region, and a gate over the channel region. At least an embedded contact is disposed atop the capacitor to electrically couple the drain doping region of the select transistor with the inner electrode of the capacitor.

Semiconductor device and fabrication method thereof

A method of forming a logic or memory cell with an epi-RSD width of larger than 1.3&#xd7; fin pitch and the resulting device are provided. Embodiments include a device including a RSD region formed on each of a plurality of fins over a substrate, wherein the RSD has a width larger than 1.3&#xd7; fin pitch, a TS formed on the RSD, and an ILD formed over the TS.

Device with large EPI in FinFETs and method of manufacturing

Aspects of the present invention relate to approaches for forming a semiconductor device such as a field-effect-transistor (FET) having a metal gate with improved performance. A metal gate is formed on a substrate in the semiconductor device. Further processing can result in unwanted oxidation in the metal that forms the metal gate. A reducing agent can be used to de-oxidize the metal that forms the metal gate, leaving a substantially non-oxidized surface.

Method for forming a metal gate including de-oxidation of an oxidized surface of the metal gate utilizing a reducing agent

The present disclosure relates to semiconductor structures and, more particularly, to capping structures and methods of manufacture. The structure includes: a plurality of gate structures in a first location with a first density; a plurality of gate structures in a second location with a second density different than the first density; and a T-shaped capping structure protecting the plurality of gate structures in the first location and in the second location.

Capping structure

A method includes providing a substrate with a patterned second layer over a first layer. The second layer includes a second layer opening having a first CD equal to the CD produced by a lithographic system (CD). CDis larger than a desired CD (CD). A third layer is formed to fill the opening, leaving a top surface of the second layer exposed. The second layer is removed to produce a mesa formed by the third layer. The CD of the mesa is equal to about the first CD. The mesa is trimmed to produce a mesa with a second CD equal to about CD. A fourth layer is formed to cover the first layer, leaving a top of the mesa exposed. The substrate is etched to remove the mesa and a portion of the first layer below the mesa to form an opening in the first layer with CD.

CD control

Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiOlayer; forming a metal layer over the SiOlayer; and planarizing the metal and SiOlayers down to the gate cap layer.

Siloxane and organic-based MOL contact patterning

Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a 'buffer zone' or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress, thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Through silicon via device having low stress, thin film gaps and methods for forming the same

One method disclosed herein includes, among other things, forming a process layer on a substrate, forming a carbon-containing silicon dioxide layer above the process layer and forming a patterned mask layer above the carbon-containing silicon dioxide layer. The patterned mask layer exposes portions of the carbon-containing silicon dioxide layer. A material modification process is performed on the exposed portions of the carbon-containing silicon dioxide layer to generate modified portions, and the modified portions are removed. The process layer is etched using remaining portions of the carbon-containing silicon dioxide layer as an etch mask.

Methods for forming mask layers using a flowable carbon-containing silicon dioxide material

Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a mask over an oxide layer and an underlying set of fin structures, the set of fin structures including a plurality of fins each having a substrate base and a silicide layer over the substrate base; implanting the oxide layer through an opening in the mask; removing the mask; polishing the oxide layer overlying the set of fin structures after removing the mask to expose the set of fin structures; and forming a nitride layer over the set of fin structures.

Controlling within-die uniformity using doped polishing material

Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench.

Dimension-controlled via formation processing

One illustrative method disclosed herein includes, among other things, forming a first sacrificial layer comprising amorphous silicon or polysilicon material around a fin in a lateral space between a plurality of laterally spaced apart gate structures that are positioned around the fin, performing a first selective etching process to remove a first sacrificial layer selectively relative to surrounding material so as to expose the fin in the lateral space, forming an epi material on the exposed portion of the fin, and forming a second layer of a sacrificial material above the epi material. The method also includes selectively removing the second layer of sacrificial material relative to at least the first layer of material to thereby define a source/drain contact opening that exposes the epi material and forming a self-aligned trench conductive source/drain contact structure that is conductively coupled to the epi material.

Methods of forming self-aligned contacts on FinFET devices

Methods of facilitating fabrication of circuit structures are provided which include, for instance: providing a structure with a film layer; modifying an etch property of the film layer by implanting at least one species of element or molecule into the upper portion of the film layer, the etch property of the film layer remaining unmodified beneath the upper portion; and subjecting the structure and film layer with the modified etch property to an etching process, the modified etch property of the film layer facilitating the etching process. Modifying the etch property of the upper portion of the film layer may include making the upper portion of the film layer preferentially susceptible or preferentially resistant to the etching process depending on the circuit fabrication approach being facilitated.

Facilitating etch processing of a thin film via partial implantation thereof

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Mechanicville, NY, United States of America

Huang Liu