Intel Corporation

Huang Kuang Hu

Nhon Toai Quach

Michael Paul Corwin

Sunny C Huang

Stuart E Sailer

Jeen Miin

A system for processing caches misses includes a request miss buffer, secondary miss logic, and a request identifier buffer. When a request misses in a cache, information characterizing the request is provided to the request miss buffer and the secondary miss logic. The secondary miss logic determines whether the request may be merged with a pending bus transaction, and provides the request identifier buffer with a pointer to the request information. The pointer is stored at an entry associated with the pending bus transaction. For a load request, data returned by the bus transaction is routed to a targeted register, using the request information in the request miss buffer.

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San Jose, CA, United States of America

Huang Kuang Hu