Industrial Technology Research Institute

Sunplus Technology Co., Ltd.

Huan-Pin Tseng

Yao-Tzung Wang

Kuo-Yen Fan

Paul Huang

Tai-Chung Chang

Chih-Yuan Liu

Chih-Yen Yang

Tsung-Han Chiang

In a method of automatically selecting audio format for output signal of a tuner, a SAW filter is configured to a bandwidth of 5.5 MHz for filtering IF signal so as to generate CVBS signal and SSIF signal. Then, band-pass filters are used to detect a back porch of the CVBS signal thereby determining whether signal amplitude at a center frequency of 4.43 MHz is greater than that at a center frequency of 3.58 MHz. Finally, a bandwidth of 4.5 MHz is assigned to the SAW filter for filtering the intermediate frequency signal to re-generate the CVBS signal when the amplitude at 4.43 MHz is smaller than that at 3.58 MHz. Further, a video decoder decodes the CVBS signal to determine a video format from NTSC, PAL-M, and PAL-N formats, and an audio decoder decodes the SSIF signal to determine an audio format from MN, BG, DK, and I formats.

Method and apparatus of automatically selecting audio format for output signal of a tuner in a television system

An image processing device and method is provided to reduce color artifact. A smooth unit performs a smooth operation on color signal corresponding to a pixel and adjacent pixels to generate smooth color signal. A level shifter performs a level-shifting on the smooth color signal to obtain level-shifted color signal. A color strength unit calculates a color strength indicator based on the color signal. A gray level decision unit is connected to the color strength unit for deciding whether the pixel is in a gray level region or not based on the color strength indicators of the pixel and adjacent pixels to generate a gray level indicator. An adjustment unit adjusts the smooth color signal and the level-shifted color signal based on the gray level indicator to generate an output color signal.

Image processing device and method for reducing color artifact

A shared memory management mechanism and method for a high-speed network releases network packets efficiently and maintains the requirement of First In First Out. A series of linked lists including a linked list for each output queue and a linked list of used broadcast packets aids a buffer manager in efficiently managing the buffers in the shared memory. The linked lists include a special data format that encodes the broadcast status, links, and whether the next entry in the list is for unicast or broadcast frames. A scanning procedure scans the broadcast status to efficiently release the broadcast frame buffers. A dynamic scanning procedure consumes less bandwidth than the scanning procedure to efficiently release the broadcast frame buffers.

Shared buffer management mechanism and method using multiple linked lists in a high speed packet switching system

A scheme for arbitrating access to a data bus shared among a plurality of competing sources is provided. Each competing source is assigned an adjustable priority weighting value (PWV) which is initially set to an initial value based on the bandwidth requirements of the competing source. During arbitration, the PWVs of those competing sources requesting access to the bus are compared, and the competing source with the smallest PWV is granted access. The PWV of the competing source which was granted access to the bus is reset to its initial value and the PWV of each competing source which requested, but was denied, access is reduced by one for subsequent comparisons. The arbitration scheme of the present invention is further applied to two-level arbitration. Each competing source is classified into a competing source group, and the requests from the grouped competing sources are processed by first level arbitration. First level arbitration passes one competing source for each group to a second level arbiter. The second level arbiter compares the PWVs of the competing sources resulting from first level arbitration to determine the competing source with the smallest PWV, and adjusts the PWVs after access to the bus has been granted.

Fair data bus arbitration system which assigns adjustable priority

A converter interface device transforms an incompatible first central processing unit (CPU2) chip into a chip compatible with a CPU1 chip. The CPU1 compatible chip, containing the CPU2, is interchangeable with the CPU1 chip. The converter interface device allows CPU2 to appear to a computer system as having the same pins and pin configuration as the CPU 1. The converter interface device has an address converter, a data converter and a control bus converter. These converters convert CPU2 signals into signals which are CPU1 compatible. In addition, the converter interface device has a bus decoder which decodes the converted CPU1 compatible signal of CPU2 and outputs a signal to a CPU switch unit. The CPU switch unit receives an external CPU select signal, and outputs a CPU1 and CPU2 enable/disable signals. Therefore, a computer system can be upgraded from CPU1 to CPU2, without having to discard the motherboard and software associated with the older CPU1. In addition, for a motherboard that can accommodate two or more CPUs, the converter interface device of the present invention allows having two different types of CPUs on such a motherboard, e.g., CPU1 and CPU2. The present invention further discloses a method for booting up the computer system to either CPU 1 or CPU2. Furthermore, a method for switching the computer system between CPU1 and CPU2 is disclosed.

Growing community of inventors

Hsinchu, Taiwan

Huan-Pin Tseng