Taiwan Semiconductor Manufacturing Comp. Ltd.

University of California

Huan-Neng Chen

Chewn-Pu Jou

Lan-Chou Cho

Feng Wei Kuo

William Wu Shen

Feng-Wei Kuo

Wen-Shiang Liao

Robert Bogdan Staszewski

Kuang-Kai Yen

Yen-Jen Chen

Yu-Ling Lin

Min-Hsiang Hsu

Tsung-Hsiung Lee

Hsiao-Tsung Yen

Ho-Hsiang Chen

Mei-Show Chen

Ying-Ta Lu

Hung-Chih Lin

Hao Chen

Ching-Nen Peng

Hsien-Yuan Liao

Shao-Yu Li

Ming-Chieh Liu

Lee Tsung Hsiung

Fu-Lung Hsueh

Jack Liu

Chin-Wei Kuo

Min-Chie Jeng

Tze-Chiang Huang

Shyh-An Chi

Seyednaser Pourmousavian

Min-Jer Wang

Chi-Feng Huang

Clement Hsingjen Wann

Chih-Hsin Ko

Chao-Ching Cheng

Yun-Han Lee

Chun-Chieh Lu

Hsieh-Hung Hsieh

Jun-De Jin

Weiwei Song

Chang-Fen Hu

Po-Wen Chiu

Der-Chyang Yeh

Chan-Hong Chern

Stefan Rusu

Chih-Chang Lin

Shuo-Mao Chen

Tzu-Jin Yeh

Hui Yu Lee

Bo-Ting Chen

Chia-Wei Hsu

Chien-Jung Wang

Yen-Lin Liu

Fan-Ming Kuo

I-Ting Lee

Jo-Yu Wu

Chuei-Tang Wang

Mill-Jer Wang

Ming Hsien Tsai

Wei-Li Chen

Ming-Hsien Tsai

Yung-Hsu Chuang

Masoud Babaie

Yi-Hsuan Liu

Yanghyo Kim

Chwei-Ching Chiu

Fan-ming Kuo

Tsung-Hsiung Li

Shih-Hung Lan

Shi-Hung Wang

Kyle Yen

Kuang Kai Yen

Willaim Wu Shen

Sandro Binsfeld Ferreira

Fen Wei Kuo

In some embodiments, digital logic components, such as those found in standard cells in integrated circuit devices, are used to synthesize signals with controllable waveforms that result in transmitted signals that meet certain requirements, such as above-threshold high openings and below-threshold over/under-shooting. In some embodiments, driving buffers with logic controls and delay chains are used to achieve controllable slew rates at rising and falling edges to minimize over/under shooting behavior in signals. In some embodiments, control logic and delay chains produce controllable rising/falling 'stair-type' edges to obtain optimized damping waveform.

Driving buffer with configurable slew rate for data transmission

A method of forming a semiconductor structure includes: providing a first inter-level dielectric (ILD) layer overlying a molding layer, the molding layer including a transmitter ground structure and a receiver ground structure; forming first openings through the first ILD layer to expose the transmitter and receiver ground structures; forming first lower transmitter and receiver electrodes in the first openings to be respectively coupled to the transmitter and receiver ground structures; forming a first dielectric waveguide overlying the first ILD layer, and first lower transmitter and receiver electrodes; depositing a second ILD layer overlying the first dielectric waveguide; forming second lower transmitter and receiver electrodes extending through the second ILD and respectively coupled to the transmitter and receiver ground structures; and forming a second dielectric waveguide overlying the second ILD layer and the second lower transmitter and receiver electrodes.

Semiconductor structure having multiple dielectric waveguide channels and method for forming semiconductor structure

A method of forming semiconductor device includes forming an active layer in a substrate including forming components of one or more transistors; forming an MD and gate (MDG) layer over the active layer including forming a gate line; forming a metal-to-S/D (MD) contact structure; and forming a waveguide between the gate line and the MD contact structure; forming a first interconnection layer over the MDG layer including forming a first via contact structure over the gate line; forming a second via contact structure over the MD contact structure; and forming a heater between the first and second via contact structures and over the waveguide.

Semiconductor device including waveguide heater

A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the first waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.

Optical waveguide apparatus and method of fabrication thereof

In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer.

Systems and methods for shielded inductive devices

A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Low dropout regulator circuits, input/output device, and methods for operating a low dropout regulator

A method includes: forming an interconnect structure over a semiconductor substrate. The interconnect structure includes: a magnetic core and a conductive coil winding around the magnetic core and electrically insulated from the magnetic core. The conductive coil includes horizontally-extending conductive lines and vertically-extending conductive vias electrically connecting the horizontally-extending conductive lines, wherein the magnetic core and the conductive coil are arranged in an inductor zone of the interconnect structure; and a connecting metal line adjacent to and on an outside of the inductor zone, the connecting metal line being electrical isolated from the inductor zone. The vertically-extending conductive vias include first conductive vias, second conductive vias, and a third conductive via between the first conductive vias and the second conductive vias. The connecting metal line is between, and non-overlapped with, the first conductive via and the second conductive vias vertically from a cross-sectional view.

Semiconductor package device with integrated inductor and manufacturing method thereof

Disclosed is a system and method for communication using an efficient fiber-to-chip grating coupler with a high coupling efficiency. In one embodiment, a method for communication, includes: transmitting optical signals between a semiconductor photonic die on a substrate and an optical fiber array attached to the substrate using at least one corresponding grating coupler on the semiconductor photonic die, wherein the at least one grating coupler each comprises a plurality of coupling gratings, a waveguide, a cladding layer, a first reflection layer and a second reflection layer, wherein the plurality of coupling gratings each comprises at least one step in a first lateral direction and extends in a second lateral direction, wherein the first and second lateral directions are parallel to a surface of the substrate and perpendicular to each other in a grating plane, wherein the first reflection layers are configured such that the plurality of coupling gratings is disposed between the first reflection layer and the cladding layer, wherein the second reflection layer are configured such that the cladding layer is disposed between the second reflection layer and the waveguide.

Fiber-to-chip grating coupler for photonic circuits

An optical device includes a waveguide configured to guide light, a taper integrated with the waveguide on a substrate configured for optical coupling, and an attenuator to degrade unwanted optical signal from the taper. The attenuator extends along one side of the taper, and includes one of a conductive structure, a doped structure and a refractive structure.

Optical device and method of manufacturing the same

A method includes etching a silicon layer to form a silicon slab and an upper silicon region over the silicon slab, and implanting the silicon slab and the upper silicon region to form a p-type region, an n-type region, and an intrinsic region between the p-type region and the n-type region. The method further includes etching the p-type region, the n-type region, and the intrinsic region to form a trench. The remaining portions of the upper silicon region form a Multi-Mode Interferometer (MMI) region. An epitaxy process is performed to grow a germanium region in the trench. Electrical connections are made to connect to the p-type region and the n-type region.

Germanium photodetector embedded in a multi-mode interferometer

An optical modulator includes a carrier and a waveguide disposed on the carrier. The waveguide includes a first optical coupling region, a second optical coupling region, first regions, and second regions. The first optical coupling region is doped with first dopants. The second optical coupling region abuts the first optical coupling region and is doped with second dopants. The first dopants and the second dopants are of different conductivity type. The first regions are doped with the first dopants and are arrange adjacent to the first optical coupling region. The first regions have respective increasing doping concentrations as distances of the first regions increase from the first optical coupling region. The second regions are doped with the second dopants and are arranged adjacent to the second optical coupling region. The second regions have respective increasing doping concentrations as distances of the second regions increase from the second optical coupling region.

Optical modulator and package

The present disclosure provides a crack detection unit (CDU), a semiconductor die, and a method of detecting a crack of a semiconductor die. The CDU comprises a switching circuit, a crack sensor, and a logic circuit. The switching circuit is configured to enable the crack sensor. The crack sensor is configured to be electrically connected to the switching circuit, the ground, and an operating voltage. The logic circuit is configured to be electrically connected to the switching circuit and the crack sensor, wherein the CDU is enabled based on an input of the logic circuit. The output of the logic circuit indicates whether the crack sensor contains a crack.

Crack detector units and the related semiconductor dies and methods

An integrated circuit includes first through fourth devices positioned over one or more substrates, a first radio frequency interconnect (RFI) including a first transmitter included in the first device, a first receiver included in the second device, and a first guided transmission medium coupled to each of the first transmitter and the first receiver, a second RFI including a second transmitter included in the first device, a second receiver included in the third device, and a second guided transmission medium coupled to each of the second transmitter and the second receiver, and a third RFI including a third transmitter included in the first device, a third receiver included in the fourth device, and the second guided transmission medium coupled to each of the third transmitter and the third receiver.

Integrated circuit with radio frequency interconnect

A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground. The ground shielding layer drives radiation signals received therein to ground to prevent induced noise in the first signal path.

Coaxial through via with novel high isolation cross coupling method for 3D integrated circuits

Systems and methods are provided for an integrated chip. An integrated chip includes a package substrate including a plurality of first layers and a plurality of second layers, each second layer being disposed between a respective adjacent pair of the first layers. A transceiver unit is disposed above the package substrate. A waveguide unit including a plurality of waveguides having top and bottom walls formed in the first layers of the package substrate and sidewalls formed in the second layers of the package substrate.

Multiband QAM interface for slab waveguide

Growing community of inventors

Taichung, Taiwan

Huan-Neng Chen