Industrial Technology Research Institute

Huan-Ke Chiu

Tzu-Yi Yang

Chun-Jen Chen

Tzu-Chan Chueh

Yeong-Lin Yu

Li-Ren Huang

Horng-Yuan Shih

Cihun-Siyong Gong

Jia-Hung Peng

Po-Hsun Tu

Chiou-Bang Chen

Cheng-Hsun Lin

Zen-Dar Hsu

June-Ming Hsu

An embodiment of the invention provides a liquid-level sensor to detect liquid-level information of a liquid to be tested in a container. The sensor includes an electrode, a sensing circuit, an amplifier and a controller. The electrode is disposed on the outer surface of the container, comprising a first electrode and a second electrode. The sensing circuit is coupled to a first electrode and a second electrode, and receives a clock signal to generate a first voltage signal and a second voltage signal. The amplifier receives the first voltage signal and the second voltage signal to output an output voltage. The controller acquires liquid-level information of the liquid to be tested according to the output voltage and a voltage-volume table.

Apparatus for detecting liquid level

An I/Q demodulation apparatus and method with phase scanning are provided. The demodulation apparatus includes a ring oscillator, a first latch unit, a decoding unit, a counter unit, a second latch unit, a first arithmetical unit and a second arithmetical unit. The first latch unit samples phase signals outputted from the ring oscillator. The decoding unit decodes the output of the first latch unit to correspondingly generate fine code of a first, a second, a third and a fourth codes. The counter unit counts the phase signals. The second latch unit samples the output of the counter unit to correspondingly generate coarse code of the first, the second, the third and the fourth codes. The first arithmetical unit performs an addition/subtraction operation by using the first code and the second code. The second arithmetical unit performs the addition/subtraction operation by using the third code and the fourth code.

I/Q demodulation apparatus and method with phase scanning

A digital phase-locked loop and a digital phase-frequency detector thereof are provided. The digital PFD includes a divisor switch unit, a low-resolution phase-error detecting unit, an accumulating unit, a high-resolution phase-error detecting unit, a constant unit, and a selector. The divisor switch unit receives and removes partial pulses of a feedback signal for obtaining a feedback clock. The low-resolution phase-error detecting unit detects phase error between a reference signal and the feedback clock to obtain a phase-error pulse width. The accumulating unit accumulates the feedback signal during the phase-error pulse width for obtaining an output selection signal. The high-resolution phase-error detecting unit detects phase error between the reference signal and the feedback signal to obtain a phase-error value. The constant unit provides at least one constant value. The selector selects and outputs one of the phase-error value and the constant value according to the output selection signal.

Digital phase-locked loop and digital phase-frequency detector thereof

A phase modulation method with a polar transmitter. A target frequency is first designated by comparing the RF signal with a reference frequency and the phase sample. An oscillator control word is generated based on the target frequency. A digital oscillator can modulate from a first phase to a second phase to synthesize a preliminary RF signal based on the oscillator control word. When the target frequency exceeds the modulation capability of the digital oscillator, the oscillator control word is generated based on the target frequency minus 180 degrees, and the preliminary RF signal is shifted by 180 degrees to be the RF signal having the target frequency. When the target frequency does not exceed the modulation capability of the digital oscillator, the oscillator control word is generated solely based on the target frequency to output the preliminary RF signal to be the RF signal having the target frequency.

Polar transmitter, method and apparatus for phase modulation

An all digital phase lock loop is disclosed, including a digitally controlled oscillator, a phase detector, and a loop filter. The digitally controlled oscillator is controlled by an oscillator tuning word to generate a variable signal. The oscillator tuning word includes a first tuning word and a second tuning word, where the frequency range of the digitally controlled oscillator, capable to be adjusted by the second tuning word, is broader than that capable to be adjusted by the first tuning word. The phase detector detects a phase error between the variable signal and a reference signal. The phase error is received by the loop filter to output the oscillator tuning word. The loop filter has several stages of the low pass filters and a modification circuit. The modification circuit detects two filter outputs from two low pass filters among the filters and accordingly adjusts the second tuning word.

All digital phase lock loop and method for controlling phase lock loop

A pipeline time-to-digital converter (TDC) is provided. The pipeline TDC includes a plurality of TDC cells. Each of the TDC cells includes a delay unit, an output unit and a determination unit. The delay unit receives a first clock signal and a first reference signal output from a previous stage TDC cell. The delay unit generates sampling phases in a period between a trigger edge of the first reference signal and a trigger edge of the first clock signal, and samples the first clock signal to obtain sampling values in accordance with the sampling phases. The output unit calculates the sampling values for outputting a conversion value. The determination unit uses and analyses the sampling values and the sampling phases for outputting time residue to a next stage TDC cell.

Pipeline time-to-digital converter

A programmable integer and fractional frequency divider is provided. The programmable divider divides a frequency of an input signal by a first divisor to generate an output signal, and comprises a programmable integer frequency divider and a fractional number switch. The programmable integer frequency divider divides the frequency of the input signal by a second divisor to generate the output signal, wherein the second divisor is first or second integers depending on a divisor switching signal. The fractional number switch calculates a pulse count of the output signal, and generates the divisor switching signal to switch from the first to the second integer when the pulse count of the output signal equals to a predetermined pulse count determined by a fractional part of the first divisor, and receives a fractional divisor control signal to change the predetermined pulse count, thereby changing the fractional part of the first divisor.

Programmable integer and fractional frequency divider

The present invention relates to a signal modulation loop for the multi-mode mobile communication. The adaptive up-conversion modulation loop is applied in the multi-mode mobile communication, and is used for signal integration for the communication system comprising the second generation communication system, the global system for mobile communication (GSM), and the third generation communication system, the wideband code division multiple access (WCDMA), so as to achieve the object of multi-mode communication by using a single modulation loop.

Growing community of inventors

Hsinchu County, Taiwan

Huan-Ke Chiu