Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Huan-Chieh Su

Chih-Hao Wang

Cheng-Chi Chuang

Li-Zhen Yu

Chun-Yuan Chen

Lin-Yu Huang

Zhi-Chang Lin

Kuo-Cheng Chiang

Yu-Ming Lin

Jia-Ni Yu

Wei-Hao Wu

Pei-Yu Wang

Shih-Chuan Chiu

Kuan-Ting Pan

Lo-Heng Chang

Kuan-Lun Cheng

Chia-Hao Chang

Shi Ning Ju

Jia-Chuan You

Sheng-Tsung Wang

Ting-Hung Hsu

Kuo-Cheng Ching

Ching-Wei Tsai

Chung-Wei Hsu

Yi-Hsun Chiu

Yi-Ruei Jhan

Meng-Huan Jao

Shi-Ning Ju

Chun-Hsiung Lin

Tri-Rung Yew

Yu-Xuan Huang

Shang-Wen Chang

Jui-Chien Huang

Yi-Bo Liao

Li-Yang Chuang

Jiann-Tyng Tzeng

Wei-Cheng Lin

Chien-Hsun Wang

Wei-An Lai

Chun-An Lin

Ming Chian Tsai

Clement Hsingjen Wann

Tien-Lu Lin

Mao-Lin Huang

Hou-Yu Chen

Guan-Lin Chen

Jin Cai

Fang-Wei Lee

Chia-Hsiang Chen

Kuo-cheng Chiang

Cheng-Long Chen

Ching-Hong Jiang

Hou-yu Chen

Yen-Chung Chang

Han-Yi Chen

Min-Hsuan Lu

Wei-Lun Hsu

Shih-Rung Yeh

Chung-Min Tsai

Yu-Tsung Wu

Kuo-Liang Liu

Chia-Chien Kuang

Shiang-Jie Yen

Jen-Hong Huang

Yun-Ju Fan

In a method of manufacturing a semiconductor device, a FET structure is formed over a substrate, which includes a plurality of semiconductor sheets vertically arranged over a bottom fin structure, a gate dielectric layer wrapping around each of the plurality of semiconductor sheets, a gate electrode disposed over the gate dielectric layer and a source/drain structure. A gate cap conductive layer is formed over the gate electrode, the bottom fin structure is replaced with a dielectric fin structure, spacers are formed on opposite sides of the dielectric fin structure, a trench is formed by etching the gate electrode using the dielectric fin and the spacers as an etching mask until the gate cap conductive layer is exposed, and the trench is filled with a first dielectric material.

Semiconductor device including spacers on sides of dielectric structure and manufacturing method thereof

A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Dual side contact structures for source/drain regions in semiconductor transistor devices and method of forming

A method for forming a semiconductor transistor device includes forming a channel structure, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a gate contact, and a back-side source/drain contact. The channel structure is formed by forming a stack of semiconductor layers. The gate structure is formed wrapping around the channel structure. The first source/drain epitaxial structure and the second source/drain epitaxial structure are formed on opposite endings of the channel structure. The gate contact is formed on the gate structure. The back-side source/drain contact is formed under the first source/drain epitaxial structure. The second source/drain epitaxial structure is formed to have a concave bottom surface.

Drain side recess for back-side power rail device

Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

Integrated circuits with finFET gate structures

A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.

Multi-gate device and related methods

A method of fabricating a semiconductor device includes providing a dummy structure including channel layers disposed over a frontside of a substrate, inner spacers disposed between adjacent channels of the channel layers and at lateral ends of the channel layers, and a gate structure interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. Perform an etching process to etch the gate structure and the plurality of channel layers to form a cut region along the active edge. Deposit a conductive material in the cut region to form a conductive feature. The method further includes thinning the substrate from a backside of the substrate to expose the conductive feature and forming a backside metal wiring layer on the backside of the substrate. The backside metal wiring layer is in electrical connection with the conductive feature.

Semiconductor device with backside power rail

A method includes forming a transistor over a substrate; forming a front-side interconnection structure over the transistor; after forming the front-side interconnection structure, removing the substrate; after removing the substrate, forming a backside via to be electrically connected to the transistor; depositing a dielectric layer to cover the backside via; forming an opening in the dielectric layer to expose the backside via; forming a spacer structure on a sidewall of the opening; after forming a spacer structure, forming a conductive feature in the opening to be electrically connected to the backside via; and after forming the conductive feature, forming an air gap in the spacer structure.

Integrated circuit structure with backside interconnection structure having air gap

Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line in a direction parallel to a backside surface of the first dielectric layer.

Spacers for semiconductor devices including backside power rails

A semiconductor device includes a plurality of stacks that each includes a plurality of nanostructures stacked over each other, a gate structure wrapping around the nanostructures and extending between the stacks, source and drain structures, and a plurality of fin structures respectively disposed on the stacks. A first surface of the gate structure between the stacks is substantially coplanar with first surfaces of the fin structures facing to the nanostructures or between the first surfaces of the fin structures and the nanostructures.

Fins disposed on stacks of nanostructures where the nanostructures are wrapped around by a gate

A semiconductor structure is provided, and includes a first fin structure, a second fin structure, and a third fin structure over a substrate. The second fin structure is located between the first fin structure and the third fin structure. The semiconductor structure also includes a fin isolation structure formed between the first fin structure and the third fin structure; and a gate structure formed over the first fin structure, the second fin structure, the third fin structure and the fin isolation structure. The semiconductor structure further includes a plurality of epitaxial structures formed over the first fin structure, the second fin structure and the third fin structure. The semiconductor structure includes a dielectric material over the first epitaxial structure, the second epitaxial structure, and the third epitaxial structure; and a contact formed in the dielectric material and connected to the first epitaxial structure and the third epitaxial structure.

Semiconductor structure and method for forming the same

A method includes forming a semiconductor strip and semiconductor layers vertically stacked over a front side of the semiconductor strip; forming a gate structure over the semiconductor layers; etching the semiconductor strip to form recesses in the semiconductor strip and on opposite sides of the gate structure; forming epitaxial layers in the recesses, respectively; forming isolation layers over the epitaxial layers, respectively; forming epitaxial source/drain structures over the isolation layers, respectively; performing an etching process from a backside of the semiconductor strip to form a via opening extending through the semiconductor strip, one of the epitaxial layer, and one of the isolation layer, wherein one of the epitaxial source/drain structures is exposed through the via opening; and forming a backside via in the via opening.

Semiconductor transistor device includes backside via electrically connecting epitaxial source/drain structures and method for forming the same

A method of forming a semiconductor transistor device. The method comprises forming a channel structure over a substrate and forming a first source/drain structure and a second source/drain structure on opposite sides of the fin structure. The method further comprises forming a gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain structure and the second source/drain structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.

Method for forming long channel back-side power rail device

The present disclosure relates to a semiconductor device having a backside source/drain contact, and method for forming the device. The semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature.

Semiconductor devices with backside power rail and methods of fabrication thereof

A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a first via disposed under and electrically connected to the first source/drain feature; and a power rail disposed under and electrically connected to the first via.

Semiconductor devices with backside power rail and method thereof

A device includes a substrate and a transistor on the substrate. The transistor includes a channel region that has at least one semiconductor nanostructure, and a gate electrode. A source/drain region is disposed adjacent to a first side of the channel region along a first direction. A hybrid fin structure is disposed adjacent to a second side of the channel region along a second direction that is transverse to the first direction. The hybrid fin structure includes a first hybrid fin dielectric layer and a second hybrid fin dielectric layer. The first and second hybrid fin dielectric layers include silicon, oxygen, carbon and nitrogen and have a different concentration of at least one of silicon oxygen, carbon, or nitrogen from one another.

Semiconductor device having dielectric hybrid fin

Growing community of inventors

Changhua County, Taiwan

Huan-Chieh Su