Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Huan-Chieh Su

Chih-Hao Wang

Cheng-Chi Chuang

Li-Zhen Yu

Chun-Yuan Chen

Lin-Yu Huang

Zhi-Chang Lin

Yu-Ming Lin

Kuo-Cheng Chiang

Jia-Ni Yu

Wei-Hao Wu

Pei-Yu Wang

Shih-Chuan Chiu

Kuan-Ting Pan

Lo-Heng Chang

Kuan-Lun Cheng

Chia-Hao Chang

Shi Ning Ju

Jia-Chuan You

Ting-Hung Hsu

Ching-Wei Tsai

Chung-Wei Hsu

Yi-Hsun Chiu

Sheng-Tsung Wang

Kuo-Cheng Ching

Yi-Ruei Jhan

Meng-Huan Jao

Shi-Ning Ju

Chun-Hsiung Lin

Tri-Rung Yew

Shang-Wen Chang

Jui-Chien Huang

Yi-Bo Liao

Li-Yang Chuang

Jiann-Tyng Tzeng

Wei-Cheng Lin

Yu-Xuan Huang

Chien-Hsun Wang

Wei-An Lai

Chun-An Lin

Ming Chian Tsai

Clement Hsingjen Wann

Tien-Lu Lin

Hou-Yu Chen

Mao-Lin Huang

Guan-Lin Chen

Fang-Wei Lee

Jin Cai

Chia-Hsiang Chen

Cheng-Long Chen

Ching-Hong Jiang

Yen-Chung Chang

Hou-yu Chen

Han-Yi Chen

Min-Hsuan Lu

Wei-Lun Hsu

Shih-Rung Yeh

Chung-Min Tsai

Yu-Tsung Wu

Kuo-Liang Liu

Chia-Chien Kuang

Shiang-Jie Yen

Jen-Hong Huang

Yun-Ju Fan

A semiconductor device includes a plurality of stacks that each includes a plurality of nanostructures stacked over each other, a gate structure wrapping around the nanostructures and extending between the stacks, source and drain structures, and a plurality of fin structures respectively disposed on the stacks. A first surface of the gate structure between the stacks is substantially coplanar with first surfaces of the fin structures facing to the nanostructures or between the first surfaces of the fin structures and the nanostructures.

Fins disposed on stacks of nanostructures where the nanostructures are wrapped around by a gate

A semiconductor structure is provided, and includes a first fin structure, a second fin structure, and a third fin structure over a substrate. The second fin structure is located between the first fin structure and the third fin structure. The semiconductor structure also includes a fin isolation structure formed between the first fin structure and the third fin structure; and a gate structure formed over the first fin structure, the second fin structure, the third fin structure and the fin isolation structure. The semiconductor structure further includes a plurality of epitaxial structures formed over the first fin structure, the second fin structure and the third fin structure. The semiconductor structure includes a dielectric material over the first epitaxial structure, the second epitaxial structure, and the third epitaxial structure; and a contact formed in the dielectric material and connected to the first epitaxial structure and the third epitaxial structure.

Semiconductor structure and method for forming the same

A method includes forming a semiconductor strip and semiconductor layers vertically stacked over a front side of the semiconductor strip; forming a gate structure over the semiconductor layers; etching the semiconductor strip to form recesses in the semiconductor strip and on opposite sides of the gate structure; forming epitaxial layers in the recesses, respectively; forming isolation layers over the epitaxial layers, respectively; forming epitaxial source/drain structures over the isolation layers, respectively; performing an etching process from a backside of the semiconductor strip to form a via opening extending through the semiconductor strip, one of the epitaxial layer, and one of the isolation layer, wherein one of the epitaxial source/drain structures is exposed through the via opening; and forming a backside via in the via opening.

Semiconductor transistor device includes backside via electrically connecting epitaxial source/drain structures and method for forming the same

A method of forming a semiconductor transistor device. The method comprises forming a channel structure over a substrate and forming a first source/drain structure and a second source/drain structure on opposite sides of the fin structure. The method further comprises forming a gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain structure and the second source/drain structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.

Method for forming long channel back-side power rail device

The present disclosure relates to a semiconductor device having a backside source/drain contact, and method for forming the device. The semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature.

Semiconductor devices with backside power rail and methods of fabrication thereof

A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a first via disposed under and electrically connected to the first source/drain feature; and a power rail disposed under and electrically connected to the first via.

Semiconductor devices with backside power rail and method thereof

A device includes a substrate and a transistor on the substrate. The transistor includes a channel region that has at least one semiconductor nanostructure, and a gate electrode. A source/drain region is disposed adjacent to a first side of the channel region along a first direction. A hybrid fin structure is disposed adjacent to a second side of the channel region along a second direction that is transverse to the first direction. The hybrid fin structure includes a first hybrid fin dielectric layer and a second hybrid fin dielectric layer. The first and second hybrid fin dielectric layers include silicon, oxygen, carbon and nitrogen and have a different concentration of at least one of silicon oxygen, carbon, or nitrogen from one another.

Semiconductor device having dielectric hybrid fin

A semiconductor device structure includes a source/drain (S/D) feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a first silicide layer in contact with the first surface of the S/D feature, a second silicide layer opposing the first silicide layer and in contact with the second surface of the S/D feature, a front side S/D contact in contact with the first silicide layer, a back side S/D contact in contact with the second silicide layer, a semiconductor channel layer comprising a sidewall in contact with the sidewall of the source/drain feature, a gate dielectric layer surrounding exposed surfaces of the semiconductor layer, an interlayer dielectric (ILD) disposed adjacent to the gate dielectric layer, and a liner disposed between and in contact with the ILD and the gate dielectric layer.

Semiconductor device with backside power rail and methods of fabrication thereof

A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.

Source/drain contacts and methods of forming same

A method for forming a semiconductor device includes followings. A transistor is formed, and the transistor is embedded in a dielectric layer and disposed over a semiconductor substrate. A first gate cutting process is performed to form a first opening in the dielectric layer. An insulator post is formed in the first opening. A second gate cutting process is performed to form a second opening in the dielectric layer. A power via is formed in the second opening. A conductor is formed, wherein the conductor is embedded in the semiconductor substrate, and the conductor is located under and electrically connected to the power via.

Method for forming semiconductor device

A device includes a substrate. A channel region of a transistor overlies the substrate and a source/drain region is in contact with the channel region. The source/drain region is adjacent to the channel region along a first direction. A source/drain contact is disposed on the source/drain region. A gate electrode is disposed on the channel region and a gate contact is disposed on the gate electrode. A first low-k dielectric layer is disposed between the gate contact and the source/drain contact along the first direction.

Semiconductor device having a gate contact on a low-k liner

A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The semiconductor device structure includes a first source/drain (S/D) structure formed adjacent to the gate structure, and a first S/D contact structure formed over the first S/D structure. The semiconductor device structure includes a first filling layer formed over the first S/D structure, and the first S/D contact structure is surrounded by the first filling layer. The semiconductor device structure includes a dielectric layer formed adjacent to the gate structure and the first filling layer, and the dielectric layer and the first filling layer are made of different materials. The first filling layer is surrounded by the dielectric layer.

Semiconductor device structure and method for forming the same

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes first nanostructures surrounded by a first gate structure, and a first source/drain (S/D) structure adjacent to the first gate structure. The semiconductor structure includes a first contact structure formed over a first side of the first S/D structure, and a second contact structure formed over a second side of the first S/D structure. The second contact structure includes a first portion and a second portion. The first portion and the second portion are made of different materials. The first S/D structure has a first width. The second portion has a second width. The first width is smaller than the second width.

Semiconductor structure having second contact structure over second side of first S/D structure

A device includes a substrate and a gate structure wrapping around at least one vertical stack of nanostructure channels. The device includes a source/drain region abutting the gate structure, and a source/drain contact over the source/drain region. The device includes an etch stop layer laterally between the source/drain contact and the gate structure and having a first sidewall in contact with the source/drain contact, and a second sidewall opposite the first sidewall. The device includes a source/drain contact isolation structure embedded in the source/drain contact and having a third sidewall substantially coplanar with the second sidewall of the etch stop layer.

Field effect transistor with source/drain contact isolation structure and method

A semiconductor device structure includes a first channel structure and a second channel structure over a substrate. The semiconductor device structure also includes a first gate stack over the first channel structure and a second gate stack over the second channel structure. The first gate stack and the second gate stack have a first work function layer and a second work function layer, respectively. The first work function layer and the second work function layer are made of a same material. The second gate stack has a first protruding portion and a second protruding portion, and each of the first protruding portion and the second protruding portion extends upwards and extend away from the second channel structure. The first protruding portion and the second protruding portion are spaced apart from each other, and half of the first gate stack is wider than the first protruding portion.

Semiconductor device structure with metal gate stack

Growing community of inventors

Changhua County, Taiwan

Huan-Chieh Su