Taiwan Semiconductor Manufacturing Comp. Ltd.

Huan-Chi Tseng

Yu-Hua Lee

Chia-Hung Lai

Min Cao

Tzong-Sheng Chang

Chia-Hsiang Chen

Han-Liang Tseng

Jiunn-Jyi Lin

Chin-Tien Yang

Yen-Ming Chen

Heng-Hsin Liu

Dian-Hau Chen

Chun-Hung Lin

Kang-Min Kuo

Yu-Chang Jong

Chien-Chang Lee

Kuan-Miao Liu

Tsong-Yuan Chen

Chih-Yang Wang

Tin-Lin Tsai

Ssu-Chia Huang

Hong-Miao Chen

Shu-Cheng Kuo

Kun-Cheng Huang

Jhy-Chen You

A device includes a test unit in a die. The test unit includes a physical test region including an active region, and a plurality of conductive lines over the active region and parallel to each other. The plurality of conductive lines has substantially a uniform spacing, wherein no contact plugs are directly over and connected to the plurality of conductive lines. The test unit further includes an electrical test region including a transistor having a gate formed of a same material, and at a same level, as the plurality of conductive lines; and contact plugs connected to a source, a drain, and the gate of the transistor. The test unit further includes an alignment mark adjacent the physical test region and the electrical test region.

Integrated circuit test units with integrated physical and electrical test regions

A dummy via design for a dual damascene structure has a dielectric layer on a substrate, a dual damascene structure filled with a conductive material and inlaid in the dielectric layer, and a dummy via structure filled with a non-conductive material and inlaid in the dielectric layer. The dummy via structure has at least two dummy vias filled with the non-conductive material and located adjacent to two sides of the dual damascene structure respectively.

Dummy via for reducing proximity effect and method of using the same

A method for fabricating a microelectronic fabrication employs an undoped silicate glass layer as an etch stop layer when etching a doped silicate glass layer with an anhydrous hydrofluoric acid etchant. The method is particularly useful for forming a patterned salicide blocking dielectric layer when fabricating a complementary metal oxide semiconductor device.

Laminated silicate glass layer etch stop method for fabricating microelectronic product

A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.

Bond pad scheme for Cu process

The invention describes how contaminant particles may be removed from a surface without in any way damaging that surface. First, the positional co-ordinates of all particles on the surface are recorded. Optionally, only particles that can be expected to cause current or future damage to the surface are included. Then, using optical tweezers, each particle is individually removed and then disposed of. Six different ways to remove and dispose of particles are described.

Contaminant particle removal by optical tweezers

An integrated de-focus pattern provides an effective in-line monitor for photo processing steps of integrated circuit wafers. The de-focus pattern is formed on an integrated circuit wafer in the vertical and horizontal spaces between integrated circuit chips. The de-focus pattern has a number of different test patterns at different heights above the wafer surface. De-focus patterns are placed across the entire wafer surface. The de-focus patterns are formed at the same time the features of the circuit chips are formed. The de-focus patterns can be analyzed optically or using a scanning electron microscope.

System for in-line monitoring of photo processing tilt in VLSI

An integrated de-focus pattern provides an effective in-line monitor of de-focus and relative tilt for photo processing steps of integrated circuit wafers. The de-focus pattern is formed on an integrated circuit wafer in the vertical and horizontal spaces between integrated circuit chips. The de-focus pattern has a number of different test patterns at different heights above the wafer surface. De-focus patterns are placed across the entire wafer surface. The de-focus patterns are formed at the same time the features of the circuit chips are formed. The de-focus patterns can be analyzed optically or using a scanning electron microscope.

System for in-line monitoring of photo processing in VLSI fabrication

Growing community of inventors

Hsin-Chu, Taiwan

Huan-Chi Tseng