International Business Machines Corporation

Samsung Electronics Co., Ltd.

Kabushiki Kaisha Toshiba

Huajie Chen

Dureseti Chidambarrao

Stephen W Bedell

Huilong Zhu

Devendra K Sadana

Bruce Bennett Doris

Keith E Fogel

Oleg Gluschenkov

Omer H Dokumaci

Werner A Rausch

Judson Robert Holt

Henry K Utomo

Dan Mihai Mocuta

Haining S Yang

Philip Joseph Oldiges

Anthony Gene Domenicucci

Dominic Joseph Schepis

Xinlin Wang

Siddhartha Panda

Richard J Murphy

Ying Di Zhang

Meikei Ieong

Kathryn Turner Schonenberg

Gregory Gower Freeman

An L Steegen

Patricia May Mooney

Sang-Hyun Oh

Tsutomu Sato

Kern Rim

Richard Stephan Wise

Wesley Charles Natzle

Andreas Daniel Stricker

Seshadri Subbanna

Diane Catherine Boyd

Anda C Mocuta

Rangarajan Jagannathan

Paul Andrew Ronsheim

Ricky S Amos

Michael Ray Sievers

David Angell

Jae-Sung Rieh

Ryan Matthew Mitchell

Omer O Dokumaci

Ghavam G Shahidi

Guy M Cohen

Kevin K Chan

Renee Tong Mo

Qiqing Christine Ouyang

Min Yang

Kenneth Jay Stein

Yanfeng Wang

Basanth Jagannathan

Michael Abramovich Gribelyuk

Daewon Yang

Fen Fen Jamin

David C Ahlgren

Woo-Hyeong Lee

David M Rockwell

Stephan W Bedell

Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a stressing layer on a substrate. The method may include doping the stressing layer with dopants. The method may include forming a silicide layer on the stressing layer. Moreover, the stressing layer may include a first lattice constant different from a second lattice constant of the substrate.

High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture

A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

High performance stress-enhanced MOSFETS using Si:C and SiGe epitaxial source/drain and method of manufacture

A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.

Ultra shallow junction formation by epitaxial interface limited diffusion

A substrate material including a Si-containing substrate and an insulating region that is resistant to Ge diffusion present atop the Si-containing substrate. The substrate material further includes a substantially relaxed SiGe alloy layer present atop the insulating region, wherein the substantially relaxed SiGe alloy layer has a planar defect density from about 5000 defects/cmor less. The substrate material may be employed in a heterostructure, in which a strained Si layer is present atop the substantially relaxed SiGe alloy layer of the substrate material.

Ion implantation for suppression of defects in annealed SiGe layers

Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

Hybrid SOI/bulk semiconductor transistors

A method for fabricating the semiconductor structure include a semiconductor substrate having a cross-section hourglass shaped channel region. A stress imparting layer is located adjacent the channel region. The hourglass shape may provide for enhanced vertical tensile stress within the channel region when it is longitudinally compressive stressed by the stress imparting layer.

Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification

Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and the recesses are filled by epitaxial deposition. The epi can be in-situ doped or subsequently implanted to form source/drain extensions. Alternatively, the etch is immediately followed by the COR pre-clean, which is followed by epitaxial deposition to fill the recesses. During the epitaxial deposition process, the deposited material is doped to form in-situ doped halos and, then, the dopant is switched to form in-situ doped source/drain extensions adjacent to the halos. Alternatively, after the in-situ doped halos are formed the deposition process is performed without dopants and an implant is used to form source/drain extensions.

Metal oxide field effect transistor with a sharp halo

A high-quality, substantially relaxed SiGe-on-insulator substrate material which may be used as a template for strained Si is described. The substantially relaxed SiGe-on-insulator substrate includes a Si-containing substrate, an insulating region that is resistant to Ge diffusion present atop the Si-containing substrate, and a substantially relaxed SiGe layer present atop the insulating region. The insulating region includes an upper region that is comprised of a thermal oxide and the substantially relaxed SiGe layer has a thickness of about 2000 nm or less.

Defect reduction by oxidation of silicon

Disclosed is a p-type field effect transistor (pFET) structure and method of forming the pFET. The pFET comprises embedded silicon germanium in the source/drain regions to increase longitudinal stress on the p-channel and, thereby, enhance transistor performance. Increased stress is achieved by increasing the depth of the source/drain regions and, thereby, the volume of the embedded silicon germanium. The greater depth (e.g., up to 100 nm) of the stressed silicon germanium source/drain regions is achieved by using a double BOX SOI wafer. Trenches are etched through a first silicon layer and first buried oxide layer and then the stressed silicon germanium is epitaxially grown from a second silicon layer. A second buried oxide layer isolates the pFET.

Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer

A structure comprises at least one transistor on a substrate, an insulator layer over the transistor, and an ion stopping layer over the insulator layer. The ion stopping layer comprises a portion of the insulator layer that is damaged and has either argon ion damage or nitrogen ion damage.

Structure and method for reducing threshold voltage variation

The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact with the insulating layer, the semiconducting layer comprising a first strained Si region and a second strained Si region; wherein the first strained Si region has a crystallographic orientation different from the second strained Si region and the first strained Si region has a crystallographic orientation the same or different from the second strained Si region. The strained level of the first strained Si region is different from that of the second strained Si region.

Strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels

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Danbury, CT, United States of America

Huajie Chen